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Chapter 12
Field-Effect Transistors
場效電晶體
Field-Effect Transistors (FETs)
•FET (場效電晶體) 是利用電場來控制電流
的大小，而且組成電流的載子僅限一種極
性，即電洞或是自由電子 。
•Metal-Oxide-Semiconductor Field-Effect
Transistor (MOSFET,金氧半場效電晶體）
可分為NMOS (以電子為電流載子)與
PMOS(以電洞為電流載子) 。
•MOSFET 包含source (源極)、gate (閘極)
、drain(汲極)及body(基座) 。
12.1 NMOS AND PMOS
TRANSISTORS
NMOS Transistor (n-p-n)
氧化物為絕緣體，沒有電
流能進入閘極端；
(gate 閘極) (drain 汲極) 控制閘極電壓能夠調整
(source 源極)
汲極到源極的電流
(O,
氧)
(M, 金)
場效
(S, 半)
(Body 基板)
NMOS (n-channel MOS)
•NMOS 之 source (源極)與drain(汲極)為ntype 半導體， body(基座) 為p-type 半導體
， gate (閘極)為導體 。
n-p-n
NMOS 的運作 (Operation)
•NMOS 的運作可分為三區(region)
•Cutoff Region (截止區)
vGS  Vto
•Triode Region (三極區) or Linear Region
(線性區)
vGS  Vto
and
vDS  vGS  Vto
•Saturation Region (飽合區)
v  V and vDS  vGS
GS
to
 Vto
Operation in the Cutoff Region
•當閘極(gate)與源極(source)間電壓vGS =0，兩個pn接面
(body-source) 與(body-drain)可視為兩個方向相反的二極
體，此時MOSFET為截止(cutoff)。
•當閘極(gate)與源極(source)間電壓vGS 逐漸上升到>Vto
(threshold voltage,臨限電壓)時，則NMOS才會開始導通。
iD  0 for vGS  Vto
Operation in the Triode Region
vGS  Vto
and
vDS  vGS  Vto
•當閘極(gate)帶正電時，可逐漸吸引自由電子聚集
在絕緣層的下方， 並將電洞推離絕緣層下方。
vGD  Vto vGS  vDS  Vto


vDS  0
vDS  0
 0  vDS  vGS  Vto
Operation in the Triode Region
vGS  Vto
and
vDS  vGS  Vto
•當閘極(gate)與源極(source)間電壓vGS 逐漸上升到>Vto
(threshold voltage,臨限電壓)，且在drain和source之間加
有電壓vDS，則形成n-type通道(channel)，通道中的自由
電子受到外加電場的驅動，形成汲極電流(drain
current)iD，其方向從drain流向source，和通道中的電子
流方向相反。
•當vDS很小時， iD與vDS成正比， 亦與vGS - Vto成正比。
•由於有氧化絕緣層，故閘極電流 iG ＝ 0。
vDS  vGS  Vto  vGS  vDS  Vto  vGD  Vto
Operation in the Triode Region
•In the triode region, the NMOS behaves as a resistor
connected between drain and source, but the resistance
decreases as vGS increases.


0, if vDS~0

iD  K 2 vGS  Vto vDS  v ,
2
DS
W
K 
L
 KP

 2
Device parameter
Operation in the Saturation Region
vGS  Vto
and
vDS  vGS  Vto
•當drain和source之間電壓vDS≥ vGS - Vto(or vGD≤ Vto) 則ntype通道在drain端寬度變為0 ，vDS再變大， iD不再上升
， 稱為飽合區。
Operation in the Saturation Region

iD  K vGS  Vto

2
Boundary between Triode and
Saturation Regions
At boundary, 使得n-type通道在drain端寬度剛好為0
vGD  Vto
vGS  vDS  Vto
代入I-V equation in saturation region
iD  Kv
2
DS

iD  K vGS  Vto
( vGS  Vto  vDS )

2
Boundary between Triode and
Saturation Regions
將
vGS  Vto  vDS
代入I-V equation in triode region


iD  K 2 vGS  Vto vDS  v

iD  K 2v  v
兩者結果一樣。
2
DS
2
DS
  Kv
2
DS
2
DS

boundary
Example 12.1
A NMOS transistor W=160um, L=2um, KP=50uA/V2, and
Vto=2 V. Plot the drain characteristic curves to scale for
vGS=0, 1,2, 3, 4, and 5 V.
1. 求 K
W KP
K ( )
 2mA / V 2
L 2
2. 求 boundary
2
iD  Kv 2 DS  2 10 3  vDS
3. 求 saturation currents
3
iD  K (vGS  Vto )  2 10  (vGS  2)
2
iD  18mA for vGS  5V
iD  8mA for vGS  4V
iD  2mA for vGS  3V
iD  0mA for vGS  2V
2
4. Plot characteristics in the triode region (parabola 拋物線).



iD  K 2 vGS  Vto vDS  v ,
2
DS
PMOS
•PMOS 之 source 與drain為p-type 半導體，
body為n-type 半導體， gate (閘極)為導體 。
•以電洞為電流載子。
MOSFET Summary
12.2 LOAD-LINE ANALYSIS OF
A SIMPLE NMOS AMPLIFIER
12.2 LOAD-LINE ANALYSIS OF
A SIMPLE NMOS AMPLIFIER
•VGG (dc source) 對NMOS 產生偏壓(bias) ，
決定操作點， 當ac input 在操作點附近隨時
間變化，導致vGS, iD亦隨時間改變。
•iD隨時間改變，導致RD亦上的壓降隨時間改
變， 使得vDS產生 ac output。
KVL
vGS (t )  vin (t )  VGG  sin( 2000t )  4
vDD  RDiD (t )  vDS (t )
Load-line equation
20  iD (t )(mA)  vDS (t )
Load-line 兩端點
(vDS  0V, iD  20mA)
(vDS  20V, iD  0mA)
•Quiescent operation point (Q point) is at vin=0.
vGS  VGG  4V
I DQ  9mA
 vGS (t )  vin (t )  VGG  sin( 2000t )  4
VGS max  5V(point A)
VGS min  3V(point B)
1V
VGSQ=4
5V
VDQ=11
7V
Distortion (變形)
Distortion
Distortion is due to that the characteristic
curves for the FET are not uniformly
spaced.
If a much smaller input amplitude was
applied we would have amplification
without appreciable distortion.
12.3 Bias Circuits
Amplifier Analysis
Amplifier analysis has two steps:
1. Determine the Q point.
2. Use a small-signal equivalent circuit to
determine impedances and gains.
The Fixed- Plus Self-Bias
Circuit
VG
vDS ?
The Fixed- Plus Self-Bias Circuit
1. Thévenin equivalent
VG  VDD
VG
R2
R1  R2
R1 R2
RG 
R1  R2
2. KVL
iD
vGS
VG  vGS  RsiD ( iG  0)
3. Usually, transistor
operates in saturation region
iD  K (vGS  Vto ) 2
4. Load Line Analysis iD vs. vGS
vGS  Vto
turn off
vGS  Vto
saturation
VG  vGS  RsiD
iD  K (vGS  Vto )
2
5. Determine vDS
iD
vDS  vDD  ( RD  Rs )iD
Example 12.2
Analyze the following circuit. The transistor KP=50uA/V2,
Vto=2 V, L=10um, W=400um
1. Determine K
W KP
K ( )
 1mA / V 2
L 2
2. Thévenin equivalent
VG  VDD
R2
1
 20
 5V
R1  R2
3 1
3. Determine VGSQ
VG  VGSQ  Rs I DQ
I DQ  K (VGSQ  Vto ) 2
VG  VGSQ  Rs K (VGSQ  Vto )2
2
VGSQ
(
1
V
 2Vto )VGSQ  Vto2  G  0
Rs K
Rs K
2
VGSQ
 3.630VGSQ  2.148  0
VGSQ  2.886 or 0.744
×
4. IDQ & VDSQ
I DQ  K (VGSQ  Vto )  0.784mA
2
VDSQ  VDD  ( RD  Rs ) I DQ  14.2V
12.4 SMALL-SIGNAL
EQUIVALENT CIRCUITS
iD t   I DQ  id t  Small signal (ac)
vGS t   VGSQ  v gs t 
Small signal (ac)
To determine vgs(t) vs. id(t)
 iD  K (vGS  Vto ) 2 for satutation
I DQ  id (t )  K[VGSQ  vgs (t )  Vto ]2
2
 K (VGSQ  Vto )2  2K (VGSQ  Vto )vgs (t )  Kvgs
(t )
SMALL-SIGNAL EQUIVALENT
CIRCUITS
2
I DQ  id (t )  K (VGSQ  Vto )2  2K (VGSQ  Vto )vgs (t )  Kvgs
(t )
At Q point
I DQ  K (VGSQ  Vto ) 2
2
(2K (VGSQ  Vto )vgs (t )  Kvgs
(t ))
0
I DQ  id (t )  K (VGSQ  Vto )  2K (VGSQ  Vto )vgs (t )  Kv (t )
2
2
gs
id (t )  2 K (VGSQ  Vto )vgs (t )  g m vgs (t )
g m  2 K (VGSQ  Vto )
 2 KI DQ
 2 KP W / L I DQ
W
K 
L
 KP

 2
12.5 Common Source
Amplifiers
vin?
vo ?
Voltage gain
Av=vo/ vin?
Common-Source Amplifiers
•C1 and C2 are coupling capacitors and Cs is
the bypass capacitor. The capacitors are
intended to have large impedances for the dc
signal and very small impedances for the ac
signal.
1
Zc 
j 2fC
 Zc  , f  0

 Zc  0, f  0, or C is large
Common-Source Amplifiers
•For DC analysis, the capacitors are replaced
by open circuits to determine the quiescent
operation point (Q point). The
transconductance gm for the small-signal
equivalent circuit is also determined.
•For AC analysis, the capacitor are replaced
by short circuits to determine the ac voltage
gain Av=vo/vin.
DC Analysis
Coupling capacitors
DC voltage sources
Bypass capacitors
The Small-Signal Equivalent
Circuit
•In small-signal midband analysis of FET
amplifiers, the coupling capacitors, bypass
capacitors, and dc voltage sources are
replaced by short circuits.
•The FET is replaced with its small-signal
equivalent circuit. Then, we write circuit
equations and derive useful expressions for
gains, input impedance, and output
impedance.
AC Analysis
DC voltage sources
Coupling capacitors
Bypass capacitors
DC voltage sources
Coupling capacitors
Bypass capacitors
SMALL-SIGNAL EQUIVALENT
CIRCUITS (12.4)
id (t )  g m v gs (t )
A more complex equivalent circuit consider drain resistance rd
1 rd 
id (t )  g m vgs (t )  vds / rd
iD
v DS
Q  point
Common Source Amplifiers: FET source 端接ground
Common Source Amplifiers:
Equivalent load resistance
1
RL 
1 rd  1 RD  1 RL
Input voltage & output voltage
vo   g m v gs RL

vin  v gs
Voltage Gain
vo
Av 
  g m RL
vin
Common Source Amplifiers:
Input Resistance
vin
Rin 
 RG  R1 R2
iin
Output resistance
•disconnect the load,
•replace the signal source by
the internal resistance,
• find the resistance by looking
into the output terminals.
1
Ro 
1 RD  1 rd
Example 12.4
Analyze the following circuit. KP=50uA/V2, Vto=2 V,
L=10um, W=400um (identical to example 12.2).
Assume
v(t )  100 sin( 2000t )mV

rd  
Find
•midband voltage gain
•input resistance
•output resistance
•output voltage
Example 12.4
Analyze the following circuit. KP=50uA/V2, Vto=2 V,
L=10um, W=400um (identical to example 12.2).
DC Analysis
Fine Q point (see example 12.2)
I DQ  K (VGSQ  Vto )2  0.784mA
Example 12.4
Analyze the following circuit. KP=50uA/V2, Vto=2 V,
L=10um, W=400um (identical to example 12.2).
AC Analysis
Fine gm(see Ch 12.4)
g m  2 K (VGSQ  Vto )  2 KP W / L I DQ  1.77mS
Equivalent load resistance
1
RL 
 3197
1 rd  1 RD  1 RL
Voltage Gain
( rd   )
vo
Av 
  g m RL  5.66
vin
Example 12.4
Analyze the following circuit. KP=50uA/V2, Vto=2 V,
L=10um, W=400um (identical to example 12.2).
Input Resistance
vin
Rin 
 RG  R1 R2  750k
iin
1
 RD  4.7 k
1 RD  1 rd
Rin
vin (t )  vgs (t )  v(t )
 88.23 sin( 2000t )mV
Rin  R
Output Resistance R 
o
Input voltage
Output voltage
vo (t )  Av vin (t )  500 sin( 2000t )mV
12.7 CMOS Logic Gate
CMOS: Complementary Metal-Oxide- Semiconductor (互補
式金氧半導體是一種積體電路製程，可在矽晶圓上製作出
PMOS（P-channel MOSFET）和NMOS（N-channel
MOSFET）元件，由於PMOS與NMOS在特性上為互補性
，因此稱為CMOS。
MOSFET Summary
VGS=VDD (high)
VGS= −VDD
NMOS ON
PMOS ON
VGS=0 (low)
NMOS OFF
VGS=0
PMOS OFF
CMOS Inverter
NMOS VGS=Vin
Vin=VDD (high)
PMOS VGS= Vin -VDD
NMOS VGS= VDD ON,
PMOS VGS= 0 OFF,
Vout=0 (low)
Vin=0 (low)
NMOS VGS= 0 OFF
PMOS VGS= -VDD ON,
Vout= VDD (high)
CMOS NAND Gate
1. A= high & B= high
M1 and M2 OFF
M3 and M4 ON
Vout low
2. A= low & B= low
M1 and M2 ON
M3 and M4 OFF
Vout high
CMOS NAND Gate
3. A= high & B= low
M1 OFF and M2 ON
M3 ON and M4 OFF
Vout high
4. A= low & B= high
M1 ON and M2 OFF
M3 OFF and M4 ON
Vout high
CMOS NOR Gate
1. A= low & B= low
3. A= high & B= high
M1 and M2 ON
M1 and M2 OFF
M3 and M4 OFF
M3 and M4 ON
Vout high
Vout low
2. A= high & B= low
M1 and M4 OFF
M2 and M3 ON
Vout low