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2 ASIC Design Methodology
Contents
1) Definition
2) Design Representation(Top-down, B-S-P)
3) Design Objectives
4) ASIC Types
5) ASIC Design Process
6) Cost Analysis
Lecture_2 #1
1) Definition of ASIC
 ASIC is application-specific.
(vs. General-Purpose, Commodity or Standard IC i.e., memory,
microprocessor)
 ASIC can become ASSP(Application-Specific Standard Product) if
volume becomes large.(ex:MODEM, disk controller)
 ASIC integrates many block in one chip.
(Today’s board is tomorrow’s ASIC.)
Lecture_2 #2
2) Design Representation using Gajski’s Y-chart
Lecture_2 #3
3) Design Objectives
low
performance
FPGA
Gate array
CBIC
NRE Cost
Full-custom
long
high
PTAT(Product
Turn-around Time)
Per-chip
cost(chip area)
high
Lecture_2 #4
4) ASIC Types
 PLD
PAL(device name), PLA(circuit style) ;
all AND-OR plane logic(two-level logic)
 FPGA
Semi-custom
IC
(ASIC in
narrow sense)
 Gate Array(with or without embedded block, ex;memory)
 Standard Cell(w. or w/o macro)
 Compiled block ; datapath, RAM, ROM, multiplier
 Full - Custom
Lecture_2 #5
Important elements in ASIC Design
System specification
in-house
CAD tools
ASIC
design
Commercial
CAD tools
IP
library
ASIC foundry
Lecture_2 #6
Programmable logic device(PLD) die.
The macrocells typically
consist of programmable
array logic followed by a
flip-flop or latch. The
macrocells are connected
using a large
programmable
interconnect block.
Lecture_2 #7
Field-programmable gate array(FPGA) die.
All FPGAs contain a
regular structure
programmable
interconnect.
Lecture_2 #8
Two-step manufacturing
Full-custom
fabrication
Semi-custom
fabrication
Standard phase
custom phase
Lecture_2 #9
Standard & Custom Masks
Two-step manufacture :
First(deep)
processing steps
Customization :
contacts & metal layers
Standard
masks
Custom
masks
Base wafers
ASIC
Lecture_2 #10
Architecture Specifications
 Master array = core + I/O pads
 Core : - macro-architecture


number & distribution of basic core cells
embedded(specialized) structures
- micro-architecture









isolation method : gate or oxide isolation
predefined channels or channelless layout
available devices : transistors, capacitors, resistors, …
NMOS/PMOS transistor count ratio
number of contacts to each transistor gate, source or drain
spacing between transistors, or transistor pitch
identical or variable size transistors
relative size of the NMOS and PMOS transistors
layout of the basic core cell
 I/O pads - number, functional capabilities, size, ...
Lecture_2 #11
Comparison of Various ASIC Methodologies
 PLDs, PALs, EPLDs :
< 2K gates
field programmable AND/OR arrays with latches
use (E)EPROM or (anti)fuse devices
 field programmable gate arrays(FPGA) :
< 5K gates(1972),  100K gates(1998)
electrically programmable SRAM, antifuse or EPROM devices
logic mapped into predefined blocks
programmable interconnections
Rapidly changing
designs
low volume
low complexity
 gate arrays, sea-of-gates(SOG) :
200K gates
personalized with metals & contacts
standard cell
compiled cells datapath, ROM, RAM
 macro-based & full-custom :
all mask layers personalized
dense & high performance
High volume
complex
stable designs
Lecture_2 #12
Field Programmable Gate Arrays
K

Fill the gap between PALs and classical(mask programmable) gate arrays

architecture :
 array of configurable logic blocks(gates, multiplexers, flip-flops)
 predefined routing channels filled with interconnection wires
 wires are programmable

programming technology : EPROM, anti-fuse, or SRAM.
 SRAM : volatile but reconfigurable configuration
 EPROM : non-volatile and reprogrammable,
 anti-fuse circuits : permanent programming


size : up to 10K gate, (now 200K gates)
speed is comparable to PALS.
Xilinx
Altera
Actel
Lecture_2 #13
First Generations of Gate Arrays
 First gate arrays :

one programmable metal layer

fixed contact locations

extensive use of polysilicon for routing

2- or 3- transistor cell -> 2- or 3-input
NAND (NOR) gates
 later improvements :
P
N
Predefined
channel

use several basic cells to implement more
complex macros

programmable contacts

second programmable metal layer + vias
P
N
Lecture_2 #14
Second Generation : Sea-of-Gates
 CHANNELLESS LAYOUT



VDD
suppression of predefeined channels
array entirely filled up with transistors
connections are routed over unused transistors
P
 GATE ISOLATION vs. OXIDE ISOLATION
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suppression of the gaps in the diffusion
continuous strips of diffusion with equally spaced
transistors
basic cell = 1N & 1P
electrical isolation made by connecting a gate to
VSS(NMOS) or VDD(PMOS)
N
VSS
Gate isolation
VDD
P
 OTHER VARIANTS & IMPROVEMENTS :


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embedded arrays
RAM-compatible basic cell
additional metal layers
N
VSS
Oxide isolationLecture_2 #15
Gate Isolation vs Oxide Isolation
 ADVANTAGES OF GATE ISOLATION :

flexibility in macro width(one transistor
increment)

density : transistor gate length smaller than
diffusion-diffusion distance

full merging of source & drain
 PROBLEMS WITH GATE ISOLATION :

N-and P-gate need to be physically separated

on very large & noisy circuits, glitches on
power supply lines may weaken the isolation
for short times
Lecture_2 #16
Channelled versus Channelless Array
Routing problem is simpler
OK with only one metal
Flexibility in channel definition(position & width)
over-the-cell routing
higher packing density
RAM-compatible
supports variable-height cells & macrocells
now universally used
Lecture_2 #17
Routing Channels
Alternate channels :

Simpler

reusability of classical P&R tools

tunable channel width(in fixed increments)

lower density(in terms of gates)

gates are smaller

smaller transistor size
Covering channels :

fixed channel width

increased master cell area

large transistor size

both methods can be used together

needs a special macro design
Lecture_2 #18
Metal Usage
 Signal routing :

internal macro connections : metal 1

external horizontal wires(channels) : metal 1

external vertical wires : metal 2

metal 3&4, if any, follow direction of metal 1&2, respectively
Lecture_2 #19
Metal Usage
 power distribution :

primary distribution : horizontal metal 1 lines

secondary distribution : vertical metal 2 lines
Lecture_2 #20
Embedded Structures
A part of the core is dedicated to a special
function
most often : static RAM but also ROM, A/D or
D/A converters, PLL, …
also : embedded test structures
advantages : optimized function, performance,
high density
drawback s : less versatile array, need to
maintain a larger master family(price !)
Core is generic and supports various
customizations
reduced master family -> lower price
higher flexibility, e.g. RAM size and location
need adapted CAD tools
Lecture_2 #21
BiCMOS Master Architecture(1)
Higher gate count(CMOS is denser)
TTL or ECL I/Os
examples :
Hitachi 84
NTT 89(reduced voltage on-chip)
now abandoned
BiCMOS periphery blocks used for
clock buffers, level conversion, …
CMOS core : 60% - 95% area
example :
LSI Direct Drive Array(88)
Lecture_2 #22
BiCMOS Master Architecture(2)
Variant of the previous
mixed digital/analog applications
bipolar part can contain passive elements
can be seen as an embedded array
example : LSI Logic
Higher flexibility in the use of both devices
full digital or mixed applications
the most used architecture
examples :
Motorola, AMCC, Hitachi, TI, Toshiba
NEC, Fujitsu
Lecture_2 #23
Standard Cell Layout(W=25mm in l=0.25mm
Lecture_2 #24
CBIC routing in 2-metal layers
Lecture_2 #25
Datapath composed of datapath cells
control and power signals (metal 2)
poly
metal 1
metal 2
Bit 31
Bit 30
Data
buses
(metal 3)
metal 3
VDD control signal
(metal 2) (metal 2)
Bit 2
Bit 1
Bit 0
VSS
(metal 2)
adder mux
Tr. gate
inv
VDD
(metal 1)
P diff.
1 bit-slice
N diff.
VSS
(metal 1)
Data Buses
(metal 3)
2-1 mux
inverter
Datapath cell = Bit Slice  Functional Element
Lecture_2 #26
5) ASIC design process
Lecture_2 #27
6) Cost Analysis
Spreadsheet for fixed cost of FPGA MGA and CBIC
Lecture_2 #28
Spreadsheet for Variable cost of FPGA MGA and CBIC
Lecture_2 #29
Product Profit Model
Lecture_2 #30