Download Slide Set 5

THE INVERTERS
DIGITAL GATES
Fundamental Parameters




Functionality
Reliability, Robustness
Area
Performance
» Speed (delay)
» Power Consumption
» Energy
Digital Integrated Circuits
Introduction
© Prentice Hall 1995
Noise in Digital Integrated Circuits
v(t)
VDD
i(t)
(a) Inductive coupling
(b) Capacitive coupling
(c) Power and ground
noise
Digital Integrated Circuits
Introduction
© Prentice Hall 1995
DC Operation:
Voltage Transfer Characteristic
V(y)
V(x)
V
OH
V(y)
f
V(y)=V(x)
V
Switching Threshold
M
VOL
VOL
V
OH
V(x)
Nominal Voltage Levels
Digital Integrated Circuits
Introduction
© Prentice Hall 1995
Mapping between analog and digital signals
"1"
V
OH
V
IH
V(y)
V
OH
Slope = -1
Undefined
Region
"0"
V
IL
V
OL
Digital Integrated Circuits
Slope = -1
VOL
V
V
IL IH
Introduction
V(x)
© Prentice Hall 1995
Definition of Noise Margins
"1"
V
OH
NMH
Noise Margin High
Noise Margin Low
NML
V
IH
Undefined
Region
V
IL
V
OL
"0"
Gate Output
Digital Integrated Circuits
Introduction
Gate Input
© Prentice Hall 1995
The Regenerative Property
...
v1
v0
v2
v3
v5
v4
v6
(a) A chain of inverters.
v1, v3, ...
v1, v3, ...
finv(v)
f(v)
f(v)
finv(v)
v0, v2, ...
v0, v2, ...
(b) Regenerative gate
Digital Integrated Circuits
(c) Non-regenerative gate
Introduction
© Prentice Hall 1995
Fan-in and Fan-out
(a) Fan-out N
M
(b) Fan-in M
N
Digital Integrated Circuits
Introduction
© Prentice Hall 1995
The Ideal Gate
Vout
Ri = 
Ro = 0
g= 
Vin
Digital Integrated Circuits
Introduction
© Prentice Hall 1995
VTC of Real Inverter
5.0
Vout (V)
4.0
NML
3.0
2.0
VM
NMH
1.0
0.0
Digital Integrated Circuits
1.0
2.0
3.0
Vin (V)
Introduction
4.0
5.0
© Prentice Hall 1995
Delay Definitions
Vin
50%
t
t
Vout
t
pLH
pHL
90%
50%
10%
tf
Digital Integrated Circuits
t
tr
Introduction
© Prentice Hall 1995
Ring Oscillator
v1
v0
v0
v2
v3
v4
v5
v5
v1
T = 2  tp N
Digital Integrated Circuits
Introduction
© Prentice Hall 1995
Power Dissipation
Digital Integrated Circuits
Introduction
© Prentice Hall 1995
CMOS INVERTER
Digital Integrated Circuits
Introduction
© Prentice Hall 1995
The CMOS Inverter:
A First Glance
VDD
Vin
Vout
CL
Digital Integrated Circuits
Introduction
© Prentice Hall 1995
CMOS Inverters
VDD
PMOS
1.2mm
=2l
Out
In
Metal1
Polysilicon
NMOS
GND
Digital Integrated Circuits
Introduction
© Prentice Hall 1995
Switch Model of CMOS Transistor
|V GS|
Ron
|VGS| > |VT|
|VGS| < |VT|
Digital Integrated Circuits
Introduction
© Prentice Hall 1995
CMOS Inverter: Steady State Response
VDD
VDD
Ron
VOH = VDD
Vout
Vout
VM = f(Ronn,Ronp)
Ron
Vin = V DD
Digital Integrated Circuits
VOL= 0
Vin = 0
Introduction
© Prentice Hall 1995
CMOS Inverter: Transient Response
VDD
tpHL = f(Ron.CL)
= 0.69 RonCL
Vout
ln(0.5)
Vout
CL
Ron
1
VDD
0.5
0.36
Vin = V DD
RonCL
Digital Integrated Circuits
Introduction
t
© Prentice Hall 1995
CMOS Properties
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Full rail-to-rail swing
Symmetrical VTC
Propagation delay function of load
capacitance and resistance of transistors
No static power dissipation
Direct path current during switching
Digital Integrated Circuits
Introduction
© Prentice Hall 1995
Voltage Transfer
Characteristic
Digital Integrated Circuits
Introduction
© Prentice Hall 1995
PMOS Load Lines
IDn
V in = V DD -VGSp
IDn = - IDp
V out = VDD -VDSp
V out
IDp
IDn
IDn
Vin=0
Vin=0
Vin=3
Vin=3
V DSp
V DSp
Vout
VGSp=-2
VGSp=-5
Digital Integrated Circuits
Vin = V DD-VGSp
IDn = - IDp
Introduction
Vout = V DD-VDSp
© Prentice Hall 1995
CMOS Inverter Load Characteristics
In,p
Vin = 5
V in = 0
NMOS
PMOS
Vin = 4
Vin = 1
Vin = 4
Vin = 3
Vin = 2
Vin = 3
Vin = 4
Vin = 2
V in = 3
Vin = 1
Vin = 0
Vin = 5
Digital Integrated Circuits
Vin = 2
Introduction
© Prentice Hall 1995
CMOS Inverter VTC
NMOS off
PMOS lin
5
Vou t
4
NMOS sat
PMOS lin
2
3
NMOS sat
PMOS sat
1
NMOS lin
PMOS sat
1
Digital Integrated Circuits
2
Introduction
3
4
NMOS lin
PMOS off
5
Vin
© Prentice Hall 1995
Simulated VTC
Vout (V)
4.0
2.0
0.0
0.0
1.0
2.0
3.0
4.0
5.0
Vin (V)
Digital Integrated Circuits
Introduction
© Prentice Hall 1995
Gate Switching Threshold
4.0
VM
3.0
2.0
1.00.1
Digital Integrated Circuits
0.3
1.0
kp/kn
Introduction
3.2
10.0
© Prentice Hall 1995
MOS Transistor Small Signal Model
G
D
+
vgs
gmvgs
ro
S
Digital Integrated Circuits
Introduction
© Prentice Hall 1995
Determining VIH and VIL
Digital Integrated Circuits
Introduction
© Prentice Hall 1995
Propagation Delay
Digital Integrated Circuits
Introduction
© Prentice Hall 1995
CMOS Inverter: Transient Response
VDD
tpHL = f(Ron.CL)
= 0.69 RonCL
Vout
ln(0.5)
Vout
CL
Ron
1
VDD
0.5
0.36
Vin = V DD
RonCL
Digital Integrated Circuits
Introduction
t
© Prentice Hall 1995
CMOS Inverter Propagation Delay
VDD
tpHL = CL Vswing/2
Iav
CL
Vout
~
Iav
CL
kn VDD
Vin = V DD
Digital Integrated Circuits
Introduction
© Prentice Hall 1995
Computing the Capacitances
VDD
VDD
M2
Vin
Cg4
Cdb2
Cgd12
M4
Vout
Cdb1
Cw
M1
Vout2
Cg3
M3
Interconnect
Fanout
Simplified
Model
Digital Integrated Circuits
Vin
Vout
CL
Introduction
© Prentice Hall 1995
CMOS Inverters
VDD
PMOS
1.2mm
=2l
Out
In
Metal1
Polysilicon
NMOS
GND
Digital Integrated Circuits
Introduction
© Prentice Hall 1995
The Miller Effect
Cgd1
V
Vout
Vout
V
Vin
V
2Cgd1
M1
V
M1
Vin
“A capacitor experiencing identical but opposite voltage swings
at both its terminals can be replaced by a capacitor to ground,
whose value is two times the original value.”
Digital Integrated Circuits
Introduction
© Prentice Hall 1995
Computing the Capacitances
Digital Integrated Circuits
Introduction
© Prentice Hall 1995
Impact of Rise Time on Delay
0.35
tpHL(nsec)
0.3
0.25
0.2
0.15
Digital Integrated Circuits
0
0.2
0.4
0.6
trise (nsec)
Introduction
0.8
1
© Prentice Hall 1995
Delay as a function of VDD
28
Normalized Delay
24
20
16
12
8
4
0
1.00
2.00
3.00
4.00
5.00
VDD (V)
Digital Integrated Circuits
Introduction
© Prentice Hall 1995
Where Does Power Go in CMOS?
• Dynamic Power Consumption
Charging and Discharging Capacitors
• Short Circuit Currents
Short Circuit Path between Supply Rails during Switching
• Leakage
Leaking diodes and transistors
Digital Integrated Circuits
Introduction
© Prentice Hall 1995
MOS Transistors (again)

Device Equations:
» Off (ignore sub-threshold): Vgs < Vt
–
Ids = 0
» Linear: Vgs > Vt & |Vdg|<|Vth|
» Saturation:Vgs>Vt & |Vgd| > |Vth|
Introduction to VLSI Design
Introduction
© Steven P. Levitan 1998
Current Flow in an Inverter
R = 100 Ohms
Introduction to VLSI Design
C = 0.1 pf (100 ff)
Introduction
© Steven P. Levitan 1998
Spice Deck
*** SPICE DECK created from inv1.sim, tech=scmos
M1 2 4 1 1 CMOSP L=3.0U W=6.0U
M2 0 4 3 0 CMOSN L=3.0U W=6.0U
R3 2 5 100
R4 3 5 100
R5 5 6 100
C6 6 0 0.1000PF
*vin 4
*vout 6
vdd 1 0 dc 5v
****************V1 V2 Del Tr Tf Tpw Period
vin 4 0 pulse (0v 5v 5ns 5ns 5ns 5ns 50ns)
Introduction to VLSI Design
Introduction
© Steven P. Levitan 1998
Dynamic Power Dissipation
Vdd
Vin
Vout
CL
Energy/transition = CL * Vdd2
Power = Energy/transition * f = CL * Vdd2 * f
Not a function of transistor sizes!
Need to reduce CL, Vdd, and f to reduce power.
Digital Integrated Circuits
Introduction
© Prentice Hall 1995
Impact of
Technology Scaling
Digital Integrated Circuits
Introduction
© Prentice Hall 1995
Technology Evolution
Digital Integrated Circuits
Introduction
© Prentice Hall 1995
Technology Scaling (1)
Minimum Feature Size
Digital Integrated Circuits
Introduction
© Prentice Hall 1995
Technology Scaling (2)
Number of components per chip
Digital Integrated Circuits
Introduction
© Prentice Hall 1995
Propagation Delay Scaling
Digital Integrated Circuits
Introduction
© Prentice Hall 1995
Technology Scaling Models
• Full Scaling (Constant Electrical Field)
ideal model — dimensions and voltage scale
together by the same factor S
• Fixed Voltage Scaling
most common model until recently —
only dimensions scale, voltages remain constant
• General Scaling
most realistic for todays situation —
voltages and dimensions scale with different factors
Digital Integrated Circuits
Introduction
© Prentice Hall 1995
Scaling Relationships for Long Channel
Devices
Digital Integrated Circuits
Introduction
© Prentice Hall 1995
Scaling of Short Channel Devices
Digital Integrated Circuits
Introduction
© Prentice Hall 1995