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Lecture 10
Wire and Via
Jan. 27, 2003
Modern VLSI Design 3e: Chapter 2
week4-1
Partly from 2002 Prentice Hall PTR
Topics
Wire and via structures.
 Wire parasitics and resistance.
 Transistor parasitics and resistance.

Modern VLSI Design 3e: Chapter 2
week4-2
Partly from 2002 Prentice Hall PTR
Wires and vias
metal 3
metal 2
vias
metal 1
poly
n+
p-tub
Modern VLSI Design 3e: Chapter 2
poly
n+
week4-3
Partly from 2002 Prentice Hall PTR
Metal migration
Current-carrying capacity of metal wire
depends on cross-section. Height is fixed,
so width determines current limit.
 Metal migration: when current is too high,
electron flow pushes around metal grains.
Higher resistance increases metal migration,
leading to destruction of wire.

Modern VLSI Design 3e: Chapter 2
week4-4
Partly from 2002 Prentice Hall PTR
Metal migration problems and
solutions
Marginal wires will fail after a small
operating period—infant mortality.
 Normal wires must be sized to accomodate
maximum current flow:

Imax = 1.5 mA/m of metal width.

Mainly applies to VDD/VSS lines.
Modern VLSI Design 3e: Chapter 2
week4-5
Partly from 2002 Prentice Hall PTR
Diffusion wire capacitance

Capacitances formed by p-n junctions:
sidewall
capacitances
depletion region
n+ (ND)
substrate (NA)
Modern VLSI Design 3e: Chapter 2
bottomwall
capacitance
week4-6
Partly from 2002 Prentice Hall PTR
Depletion region capacitance

Zero-bias depletion capacitance:
– Cj0 = si/xd.

Depletion region width:
– xd0 = sqrt[(1/NA + 1/ND)2siVbi/q].

Junction capacitance is function of voltage
across junction:
– Cj(Vr) = Cj0/sqrt(1 + Vr/Vbi)
Modern VLSI Design 3e: Chapter 2
week4-7
Partly from 2002 Prentice Hall PTR
Poly/metal wire capacitance

Two components:
– parallel plate;
– fringe.
fringe
plate
Modern VLSI Design 3e: Chapter 2
week4-8
Partly from 2002 Prentice Hall PTR
Metal coupling capacitances

Can couple to adjacent wires on same layer,
wires on above/below layers:
metal 2
metal 1
Modern VLSI Design 3e: Chapter 2
metal 1
week4-9
Partly from 2002 Prentice Hall PTR
Example: parasitic capacitance
measurement
n-diffusion: bottomwall=2 fF, sidewall=2 fF.
 metal: plate=0.15 fF,
1.5 m
fringe=0.72 fF.

3 m
0.75 m
Modern VLSI Design 3e: Chapter 2
1 m
week4-10
2.5 m
Partly from 2002 Prentice Hall PTR
Wire resistance

Resistance of any size square is constant:
Modern VLSI Design 3e: Chapter 2
week4-11
Partly from 2002 Prentice Hall PTR
Mean-time-to-failure
MTF for metal wires = time required for
50% of wires to fail.
 Depends on current density:

–
–
–
–
proportional to j-n e Q/kT
j is current density
n is constant between 1 and 3
Q is diffusion activation energy
Modern VLSI Design 3e: Chapter 2
week4-12
Partly from 2002 Prentice Hall PTR
Skin effect
At low frequencies, most of copper
conductor’s cross section carries current.
 As frequency increases, current moves to
skin of conductor.

– Back EMF induces counter-current in body of
conductor.

Skin effect most important at gigahertz
frequencies.
Modern VLSI Design 3e: Chapter 2
week4-13
Partly from 2002 Prentice Hall PTR
Effect on resistance

Low frequency resistance of wire:
– Rdc = 1/ s wt

High frequency resistance with skin effect:
– Rhf = 1/2 s d (w + t)

Resistance per unit length:
– Rac = sqrt(Rdc 2 + k Rhf 2)

Typically k = 1.2.
Modern VLSI Design 3e: Chapter 2
week4-14
Partly from 2002 Prentice Hall PTR
Review
Current characteristics
 Capacitance
 Wire and via (tub tie)

Modern VLSI Design 3e: Chapter 2
week4-15
Partly from 2002 Prentice Hall PTR
Lectures 11
Design Rule and Stick Diagram
Jan. 29, 2003
Modern VLSI Design 3e: Chapter 2
week4-16
Partly from 2002 Prentice Hall PTR
Topics
Design rules and fabrication.
 Color codes and Stick diagrams.

Modern VLSI Design 3e: Chapter 2
week4-17
Partly from 2002 Prentice Hall PTR
Why we need design rules
Masks are tooling for manufacturing.
 Manufacturing processes have inherent
limitations in accuracy.
 Design rules specify geometry of masks
which will provide reasonable yields.
 Design rules are determined by experience.

Modern VLSI Design 3e: Chapter 2
week4-18
Partly from 2002 Prentice Hall PTR
Manufacturing problems
Photoresist shrinkage, tearing.
 Variations in material deposition.
 Variations in temperature.
 Variations in oxide thickness.
 Impurities.
 Variations between lots.
 Variations across a wafer.

Modern VLSI Design 3e: Chapter 2
week4-19
Partly from 2002 Prentice Hall PTR
Transistor problems

Varaiations in threshold voltage:
– oxide thickness;
– ion implanatation;
– poly variations.
Changes in source/drain diffusion overlap.
 Variations in substrate.

Modern VLSI Design 3e: Chapter 2
week4-20
Partly from 2002 Prentice Hall PTR
Wiring problems
Diffusion: changes in doping -> variations
in resistance, capacitance.
 Poly, metal: variations in height, width ->
variations in resistance, capacitance.
 Shorts and opens:

Modern VLSI Design 3e: Chapter 2
week4-21
Partly from 2002 Prentice Hall PTR
Oxide problems
Variations in height.
 Lack of planarity -> step coverage.

metal 2
metal 2
Modern VLSI Design 3e: Chapter 2
metal 1
week4-22
Partly from 2002 Prentice Hall PTR
Via problems
Via may not be cut all the way through.
 Undesize via has too much resistance.
 Via may be too large and create short.

Modern VLSI Design 3e: Chapter 2
week4-23
Partly from 2002 Prentice Hall PTR
MOSIS SCMOS design rules
Designed to scale across a wide range of
technologies.
 Designed to support multiple vendors.
 Designed for educational use.
 Ergo, fairly conservative.

Modern VLSI Design 3e: Chapter 2
week4-24
Partly from 2002 Prentice Hall PTR
 and design rules
 is the size of a minimum feature.
 Specifying  particularizes the scalable
rules.
 Parasitics are generally not specified in
 units

Modern VLSI Design 3e: Chapter 2
week4-25
Partly from 2002 Prentice Hall PTR
Wires
6
metal 3
3
metal 2
3
metal 1
3
pdiff/ndiff
2
poly
Modern VLSI Design 3e: Chapter 2
week4-26
Partly from 2002 Prentice Hall PTR
Transistors
2
3
2
3
1
5
Modern VLSI Design 3e: Chapter 2
week4-27
Partly from 2002 Prentice Hall PTR
Vias

Types of via: metal1/diff, metal1/poly,
metal1/metal2.
4
4
1
2
Modern VLSI Design 3e: Chapter 2
week4-28
Partly from 2002 Prentice Hall PTR
Metal 3 via
Type: metal3/metal2.
 Rules:

–
–
–
–
cut: 3 x 3
overlap by metal2: 1
minimum spacing: 3
minimum spacing to via1: 2
Modern VLSI Design 3e: Chapter 2
week4-29
Partly from 2002 Prentice Hall PTR
Tub tie
4
1
Modern VLSI Design 3e: Chapter 2
week4-30
Partly from 2002 Prentice Hall PTR
Spacings
Diffusion/diffusion: 3
 Poly/poly: 2
 Poly/diffusion: 1
 Via/via: 2
 Metal1/metal1: 3
 Metal2/metal2: 4
 Metal3/metal3: 4

Modern VLSI Design 3e: Chapter 2
week4-31
Partly from 2002 Prentice Hall PTR
Overglass
Cut in passivation layer.
 Minimum bonding pad: 100 m.
 Pad overlap of glass opening: 6
 Minimum pad spacing to unrelated
metal2/3: 30
 Minimum pad spacing to unrelated metal1,
poly, active: 15

Modern VLSI Design 3e: Chapter 2
week4-32
Partly from 2002 Prentice Hall PTR
Example 1
Modern VLSI Design 3e: Chapter 2
week4-33
Partly from 2002 Prentice Hall PTR
Color codes








PolySilicon -- Red
Ndiffusion -- Green
Pdiffusion -- Brown
Metal1 -- Blue
Metal2 -- Purple
Contacts/Via -- Black “X”
Nsubstrate Contact -- Green “X”
Psubstrate Contact -- Brown “X”
Modern VLSI Design 3e: Chapter 2
week4-34
Partly from 2002 Prentice Hall PTR
Stick diagrams
A stick diagram is a cartoon of a layout.
 Does show all components/vias (except
possibly tub ties), relative placement.
 Does not show exact placement, transistor
sizes, wire lengths, wire widths, tub
boundaries.

Modern VLSI Design 3e: Chapter 2
week4-35
Partly from 2002 Prentice Hall PTR
Stick layers
metal 3
metal 2
metal 1
poly
ndiff
pdiff
Modern VLSI Design 3e: Chapter 2
week4-36
Partly from 2002 Prentice Hall PTR
Dynamic latch stick diagram
VDD
in
out
VSS
phi’
Modern VLSI Design 3e: Chapter 2
phi
week4-37
Partly from 2002 Prentice Hall PTR
Sticks design of multiplexer

Start with NAND gate:
Modern VLSI Design 3e: Chapter 2
week4-38
Partly from 2002 Prentice Hall PTR
NAND sticks
VDD
a
out
b
VSS
Modern VLSI Design 3e: Chapter 2
week4-39
Partly from 2002 Prentice Hall PTR
One-bit mux sticks
VDD
ai
bi
a
out
N1
(NAND)
b
a
out
select
select’
a
N1
(NAND)
b
out
N1
(NAND)
b
VSS
Modern VLSI Design 3e: Chapter 2
week4-40
Partly from 2002 Prentice Hall PTR
3-bit mux sticks
select’
a2
b2
a1
b1
ai
bi
ai
bi
select
select’
m2(one-bit-mux)
select’
select
m2(one-bit-mux)
select’
a0
b0
select
ai
bi
Modern VLSI Design 3e: Chapter 2
select
m2(one-bit-mux)
week4-41
VDD
oi
VSS
o2
VDD
oi
VSS
o1
VDD
oi
VSS
o0
Partly from 2002 Prentice Hall PTR
Layout design and analysis tools
Layout editors are interactive tools.
 Design rule checkers are generally batch--identify DRC errors on the layout.
 Circuit extractors extract the netlist from the
layout.
 Connectivity verification systems (CVS)
compare extracted and original netlists.

Modern VLSI Design 3e: Chapter 2
week4-42
Partly from 2002 Prentice Hall PTR
Automatic layout
Cell generators (macrocell generators)
create optimized layouts for ALUs, etc.
 Standard cell/sea-of-gates layout creates
layout from predesigned cells + custom
routing.

– Sea-of-gates allows routing over the cell.
Modern VLSI Design 3e: Chapter 2
week4-43
Partly from 2002 Prentice Hall PTR
Standard cell layout
Modern VLSI Design 3e: Chapter 2
routing area
week4-44
routing area
routing area
routing area
Partly from 2002 Prentice Hall PTR
Lecture 12
Cadence Tutorial
Jan. 31, 2003
Modern VLSI Design 3e: Chapter 2
week4-45
Partly from 2002 Prentice Hall PTR
Cadence Tutorial
Lab 1
Modern VLSI Design 3e: Chapter 2
week4-46
Partly from 2002 Prentice Hall PTR
Assignment 1
Questions: 2.1, 2.2, 2.5, 2.6, 2.7, 2.9
Due date: Feb. 12, 2003 12:00 pm
Drop off:
Modern VLSI Design 3e: Chapter 2
EC 2135
week4-47
Partly from 2002 Prentice Hall PTR
Lecture 13
Chapter 2 Review
Feb. 3, 2003
Modern VLSI Design 3e: Chapter 2
week4-48
Partly from 2002 Prentice Hall PTR
Review of Chapter 2
Digital characteristics of transistor
 Current characteristics of transistor
 Capacitance of transistor
 Wire and via
 Design rules and stick diagram

Modern VLSI Design 3e: Chapter 2
week4-49
Partly from 2002 Prentice Hall PTR
Contents of the Course
ASIC



FPGA
Transistor and Layout
Gate and Schematic
Systems and VHDL/Verilog
Modern VLSI Design 3e: Chapter 2
week4-50
Partly from 2002 Prentice Hall PTR
Examples
Modern VLSI Design 3e: Chapter 2
week4-51
Partly from 2002 Prentice Hall PTR
Modern VLSI Design 3e: Chapter 2
week4-52
Partly from 2002 Prentice Hall PTR