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Lectures 6, 7 and 8
Transistor Function
Jan. 17, 20 and 22, 2003
Modern VLSI Design 3e: Chapter 2
week3-1
Partly from 2002 Prentice Hall PTR
Topics

Previous:
– Transistor as switch
– Basic fabrication steps.
Basic Transistor function
 Basic transistor behavior.

Modern VLSI Design 3e: Chapter 2
week3-2
Partly from 2002 Prentice Hall PTR
Transistor structure
n-type transistor:
Modern VLSI Design 3e: Chapter 2
week3-3
Partly from 2002 Prentice Hall PTR
Gate voltage and the channel
Vs=0 V
Vt= 0.7 V
gate
source
drain
Vgs > = Vt
Id
gate
source
Modern VLSI Design 3e: Chapter 2
drain
week3-4
Vgs < Vt
Partly from 2002 Prentice Hall PTR
Drain current characteristics
Modern VLSI Design 3e: Chapter 2
week3-5
Partly from 2002 Prentice Hall PTR
Example 1
V gs keeps 1.5V, 2.5V, 5V
 V ds changes

Modern VLSI Design 3e: Chapter 2
week3-6
Partly from 2002 Prentice Hall PTR
Drain current

Linear region (Vds < Vgs - Vt): !!!
– Id = k’ (W/L)[(Vgs - Vt)Vds - 0.5 Vds2)]

Saturation region (Vds >= Vgs - Vt):
– Id = 0.5k’ (W/L)(Vgs - Vt) 2
Text book is wrong!!!
Modern VLSI Design 3e: Chapter 2
week3-7
Partly from 2002 Prentice Hall PTR
What is related to the characteristics
W/L ratio!!!
 V between Drain and Source
 V between Gate and Source
 Threshold voltage
 Material

Modern VLSI Design 3e: Chapter 2
week3-8
Partly from 2002 Prentice Hall PTR
Transistor layout
n-type (tubs may vary):
L
w
Modern VLSI Design 3e: Chapter 2
week3-9
Partly from 2002 Prentice Hall PTR
0.5 m transconductances
From a MOSIS process:
 n-type:
– kn’ = 73 A/V2
– Vtn = 0.7 V

p-type:
– kp’ = 21 A/V2
– Vtp = -0.8 V
Modern VLSI Design 3e: Chapter 2
week3-10
Partly from 2002 Prentice Hall PTR
Current through a transistor
Use 0.5 m parameters. Let W/L = 3/2.
Measure at boundary between linear and
saturation regions.
 Vgs = 2V:
Id = 0.5k’(W/L)(Vgs-Vt)2= 93 A

Vgs = 5V:
Id = 1 mA
Modern VLSI Design 3e: Chapter 2
week3-11
Partly from 2002 Prentice Hall PTR
Explanation

When V gs = 2V, can current go beyond 93
uA (when V ds changes)?
Modern VLSI Design 3e: Chapter 2
week3-12
Partly from 2002 Prentice Hall PTR
Example 2

When Vgs = 2 V and V ds = 2 V and 1.2 V
respectively, calculate the I ds?
– W/L = 8
– K’n= 73 uA/V^2
Modern VLSI Design 3e: Chapter 2
week3-13
Partly from 2002 Prentice Hall PTR
Example 3

Inverter: when transition time, what is the
current? (important example)
– How N and P work?

Inverter: after transition time, what is the
current?
Modern VLSI Design 3e: Chapter 2
week3-14
Partly from 2002 Prentice Hall PTR
Questions

What is the real carrier in N transistor?
Modern VLSI Design 3e: Chapter 2
week3-15
Partly from 2002 Prentice Hall PTR
Gate voltage and the channel
Vs=5 V
Vt= -0.8 V
gate
source
drain
Vgs > = Vt
Id
gate
source
Modern VLSI Design 3e: Chapter 2
drain
week3-16
Vgs < Vt
Partly from 2002 Prentice Hall PTR
Questions

What is the real carrier in P transistor?
Modern VLSI Design 3e: Chapter 2
week3-17
Partly from 2002 Prentice Hall PTR
Transistor and digital Logic

Combinational logic
– Depend on transistor & inverter

Sequential logic
– Depend on transistor & inverter
Modern VLSI Design 3e: Chapter 2
week3-18
Partly from 2002 Prentice Hall PTR
Drain current characteristics
Modern VLSI Design 3e: Chapter 2
week3-19
Partly from 2002 Prentice Hall PTR
Review

N and P transistors as switches

Fabrication process

Current Characteristics of N and P
transistors
Modern VLSI Design 3e: Chapter 2
week3-20
Partly from 2002 Prentice Hall PTR
Example 4
Modern VLSI Design 3e: Chapter 2
week3-21
Partly from 2002 Prentice Hall PTR
Lecture 9
Transistor Parasitics & Latch Up
Jan. 24, 2003
Modern VLSI Design 3e: Chapter 2
week3-22
Partly from 2002 Prentice Hall PTR
Topics
Transistor and basic fabrication steps.
 Basic Transistor function
 Basic transistor behavior.
 Latch up.

Modern VLSI Design 3e: Chapter 2
week3-23
Partly from 2002 Prentice Hall PTR
Basic transistor parasitics
Gate to substrate, also gate to source/drain.
 Source/drain capacitance, resistance.

Modern VLSI Design 3e: Chapter 2
week3-24
Partly from 2002 Prentice Hall PTR
Basic transistor capacitance
Gate capacitance Cg. Determined by active
area.
 Source/drain overlap capacitances Cgs, Cgd.
Determined by source/gate and drain/gate
overlaps. Independent of transistor L.

– Cgs = Col W

Gate/bulk overlap capacitance.
Modern VLSI Design 3e: Chapter 2
week3-25
Partly from 2002 Prentice Hall PTR
Transistor gate capacitance

Gate-source/drain overlap capacitance:
gate
source
drain
overlap
Modern VLSI Design 3e: Chapter 2
week3-26
Partly from 2002 Prentice Hall PTR
Transistor source/drain parasitics
Source/drain have significant capacitance,
resistance.
 Measured same way as for wires.
 Source/drain R, C may be included in Spice
model rather than as separate parasitics.

Modern VLSI Design 3e: Chapter 2
week3-27
Partly from 2002 Prentice Hall PTR
Transistor Resistance
R=U/I
 Future topic

Modern VLSI Design 3e: Chapter 2
week3-28
Partly from 2002 Prentice Hall PTR
Latch-up
CMOS ICs have parasitic silicon-controlled
rectifiers (SCRs).
 When powered up, SCRs can turn on,
creating low-resistance path from power to
ground. Current can destroy chip.
 Early CMOS problem. Can be solved with
proper circuit/layout structures.

Modern VLSI Design 3e: Chapter 2
week3-29
Partly from 2002 Prentice Hall PTR
Parasitic SCR
circuit
Modern VLSI Design 3e: Chapter 2
I-V behavior
week3-30
Partly from 2002 Prentice Hall PTR
Parasitic SCR structure
Modern VLSI Design 3e: Chapter 2
week3-31
Partly from 2002 Prentice Hall PTR
Solution to latch-up
Use tub ties to connect tub to power rail. Use
enough to create low-voltage connection.
Modern VLSI Design 3e: Chapter 2
week3-32
Partly from 2002 Prentice Hall PTR
Tub tie layout
p+
metal (VDD)
p-tub
Modern VLSI Design 3e: Chapter 2
week3-33
Partly from 2002 Prentice Hall PTR
Question
Why these tub ties are needed?
Modern VLSI Design 3e: Chapter 2
week3-34
Partly from 2002 Prentice Hall PTR
Modern VLSI Design 3e: Chapter 2
week3-35
Partly from 2002 Prentice Hall PTR
Modern VLSI Design 3e: Chapter 2
week3-36
Partly from 2002 Prentice Hall PTR