Download Semiconductor Memories

Semiconductor
Memories
Lecture 1: May 10, 2006
EE Summer Camp
Abhinav Agarwal
Outline
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Concept/need of memory
Parameters
Types/classification
Basic features
Basic Cell circuits
Peripheral circuitry
Concept
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Data storage essential for processing
Binary storage
Switches
Write
'0'
Read
'1'
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How do you implement this in Hardware?
Requirements
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Easy reading
Easy Writing
High density
Speed, more speed and still more speed
Memory Chip Configuration
Row Address
N bits
M
2 Cells
Din
I/O Interface
Complete Address
N+M Bits
Row Dec
Memory Cell Array
WL
Cell
DL
din
I/O Control
Dout
Control
Signals
dout
Column Dec.
Column Address
M Bits
N
2 Cells
Semiconductor Memory Classification
Read-Write Memory
Random
Access
Non-Random
Access
SRAM
FIFO
DRAM
LIFO
Non-Volatile
Read-Write
Memory
Read-Only Memory
EPROM
Mask-Programmed
E2PROM
Programmable (PROM)
FLASH
Shift Register
CAM
© Digital Integrated Circuits2nd
Memories
RAM
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Random write and read operation for any cell
Volatile data
Most of computer memory
DRAM
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Low Cost
High Density
Medium Speed
SRAM
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High Speed
Ease of use
Medium Cost
ROM
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Non-volatile Data
Method of Data Writing
Mask ROM
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Data written during chip fabrication
PROM
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Fuse ROM: Non-rewritable
EPROM: Erase data by UV rays
EEPROM: Erase and write through electrical means
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Speed 2-3 times slower than RAM
Upper limit on write operations
Flash Memory – High density, Low Cost
Basic Cells
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DRAM
SRAM
VDD
WL
WL
DL
DL
WL
DL
Static CAM Memory Cell
Bit
Bit
Bit
Bit
Bit
Word
CAM
Word
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CAM
M4
M8
M9
M6
M7
M5
CAM
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Bit
Word
CAM
S
M3
Match
int
S
M2
M1
Wired-NOR Match Line
© Digital Integrated Circuits2nd
Memories
CAM in Cache Memory
CAM
SRAM
ARRAY
ARRAY
Hit Logic
Address Decoder
Input Drivers
Address
© Digital Integrated Circuits2nd
Tag
Sense Amps / Input Drivers
Hit
R/W
Data
Memories
ROM
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Fuse ROM
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WL
EEPROM
WL
Floating Gate
DL
DL
MOS NAND ROM
V DD
Pull-up devices
BL [0]
BL [1]
BL [2]
BL [3]
WL [0]
WL [1]
WL [2]
WL [3]
All word lines high by default with exception of selected row
© Digital Integrated Circuits2nd
Memories
Non-Volatile Memories
The Floating-gate transistor (FAMOS)
Floating gate
Gate
Source
D
Drain
G
tox
tox
n+
p
n+_
S
Substrate
Device cross-section
© Digital Integrated Circuits2nd
Schematic symbol
Memories
Floating-Gate Transistor Programming
20 V
10 V
S
5V
5V
0V
20 V
D
Avalanche injection
© Digital Integrated Circuits2nd
- 5V
S
- 2.5 V
0V
D
Removing programming
voltage leaves charge trapped
S
5V
D
Programming results in
higher V T .
Memories
A “Programmable-Threshold” Transistor
© Digital Integrated Circuits2nd
Memories
Periphery
 Decoders
 Sense Amplifiers
 Input/Output Buffers
 Control / Timing Circuitry
© Digital Integrated Circuits2nd
Memories
Row Decoders
Collection of 2M complex logic gates
Organized in regular and dense fashion
(N)AND Decoder
NOR Decoder
© Digital Integrated Circuits2nd
Memories
Hierarchical Decoders
Multi-stage implementation improves performance
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WL 1
WL 0
A 0A 1 A 0A 1 A 0A 1 A 0A 1
A 2A 3 A 2A 3 A 2A 3 A 2A 3
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NAND decoder using
2-input pre-decoders
A1 A0
A0
A1
© Digital Integrated Circuits2nd
A3 A2
A2
A3
Memories
Sense Amplifiers
 DV
C
tp = ---------------Iav
large
make D V as small
as possible
small
Idea: Use Sense Amplifer
small
transition
s.a.
input
© Digital Integrated Circuits2nd
output
Memories
Sense Amp Operation
V BL
V(1)
V PRE
D V(1)
V(0)
Sense amp activated
Word line activated
© Digital Integrated Circuits2nd
t
Memories
Differential Sense Amplifier
V DD
M3
M4
y
M1
bit
SE
M2
Out
bit
M5
Directly applicable to
SRAMs
© Digital Integrated Circuits2nd
Memories
Reliability and Yield
© Digital Integrated Circuits2nd
Memories
References
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Digital Integrated Circuits, 2nd Edition, Jan Rabaey,
Anantha Chandrakasan, Borivoje Nikolic
Chapter 12 http://bwrc.eecs.berkeley.edu/IcBook/slides.htm
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Sedra & Smith, Microelectronic Circuits, 4th Edition,
Chapter 13
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Section 13.9, 13.10, 13.11, 13.12
VLSI Memory Chip Design, Kiyoo Itoh