Download Manufacturing-Aware Physical Design

Manufacturing-Aware
Physical Design
Andrew B. Kahng
Puneet Gupta
(Univ. of Calif. San Diego)
http://vlsicad.ucsd.edu
ICCAD 2003
Outline
•
•
•
•
•
•
•
•
•
Challenges
“DFM Philosophy”
Manufacturing and Variability Primer
Design for Value
Composability
Performance Impact Limited Fill Insertion
Function Aware OPC
Systematic Variation Aware STA
Futures of Mfg-Aware PD
http://vlsicad.ucsd.edu
ICCAD 2003
Printing
Layout
0.25µ
0.18µ
0.13µ
90-nm
65-nm
Figures courtesy Synopsys Inc.
http://vlsicad.ucsd.edu
ICCAD 2003
Data Volume Explosion
MEBES Data Volume (GB)
350
Number of design rules per process node
300
250
200
150
100
50
0
180nm
130nm
90nm
70nm
MEBES Data Volume vs. Technology Node
MEBES file size for one critical layer vs. technology node
http://vlsicad.ucsd.edu
ICCAD 2003
RET Layers Explosion
Number of TSMC Mask Layers Using OPC/PSM
Number of design rules per process node
70%
0%
180nm
150nm
130nm
90 nm
Source: TSMC Technology Symposium, April 22 2003
http://vlsicad.ucsd.edu
ICCAD 2003
Design Rules Explosion
700
Number of design rules per process node
600
500
400
300
200
100
0
0.35um
http://vlsicad.ucsd.edu
0.25um
180nm
150nm
130nm
90nm
ICCAD 2003
Variation: Across-Wafer Frequency
http://vlsicad.ucsd.edu
ICCAD 2003
Variation: Leakage
• Subthreshold leakage current varies exponentially
with threshold voltage: I  exp(-Vth)
• Vth = f(channel length, oxide thickness, doping)
– Most affected by variations in gate length
±100% Isub
Leakage Current (pA)
90
80
70
60
50
40
30
0.16
0.17
0.18
0.19
0.20
Drawn Gate Length (um)
Dennis Sylvester, U. Michigan
http://vlsicad.ucsd.edu
±10% Ld
ICCAD 2003
Outline
•
•
•
•
•
•
•
•
•
Challenges
“DFM Philosophy”
Manufacturing and Variability Primer
Design for Value
Composability: PSM and Assists
Performance Impact Limited Fill Insertion
Function Aware OPC
Systematic Variation Aware STA
Futures of Mfg-Aware PD
http://vlsicad.ucsd.edu
ICCAD 2003
Symptoms: Routing Rules (1)
• Minimum area rules and via stacking
– Stacking vias through multiple layers can cause minimum
area violations (alignment tolerances, etc.)
– Via cells can be created that have more metal than minimum
via overlap (used for intermediate layers in stacked vias)
• Multiple-cut vias
– Use multiple-cut vias cells to increase yield and reliability
• Can be required for wires of certain widths
– Multiple via cut patterns have different spacing rules
• Four cuts in quadrilateral; five cuts in cross; six cuts in
2x3 array; …
• With wide-wire spacing rules, complicates pin access
– Cut-to-cut spacing rules  check both cut-to-cut and metalto-metal when considering via-to-via spacing
http://vlsicad.ucsd.edu
ICCAD 2003
Symptoms: Routing Rules (2)
• Width- and Length-dependent spacing rules
– Width-dependent rules: domino effects
– Variant: “parallel-run rule” (longer parallel runs  more
spacing)
– Measuring length and width: halo rules affect computation
• Influence rules or stub rules
– A fat wire, e.g., power/ground net, will influence the spacing
rule within its surroundings  any wire that is X um away
from the fat wire needs to be at least Y um away from any
other geometry.
– Example: fat wire with thin tributaries
• bigger spacing around every wire within certain distance of the thin
tributaries
• ECO insertion of a tributary causes complications
• Strange jogs and spreading when wires enter an influenced area
http://vlsicad.ucsd.edu
ICCAD 2003
Example: LEF/DEF 5.5, April 2003
http://vlsicad.ucsd.edu
ICCAD 2003
Example: LEF/DEF 5.5, April 2003
http://vlsicad.ucsd.edu
ICCAD 2003
Symptoms: Routing Rules (3)
• Density
– Grounded metal fills (dummy fill*)
– Via isodensity rules and via farm rules (via layers must be filled
and slotted, have width-dependent spacing rule analogs, etc.)
• Non-rectilinear (-geometry) routing
– X-Architecture: http://www.xinitiative.org/
• Y-Architecture: http://vlsicad.ucsd.edu/Yarchitecture/ , LSI
Logic patents
– Landing pad shapes (isothetic rectangle vs.. octagon vs.. circle),
different spacings (~1.1x) between diagonal and Manhattan wires,
etc.
• More exceptions
– More non-default classes (timing, EM reliability, …)
• Not just power and clock
– >0.25um width may be “wide”  many exceptions
http://vlsicad.ucsd.edu
ICCAD 2003
Symptoms: Routing Rules
• Degrade completion rates, runtime
efficiency
• “Postprocessing” likely no longer suffices
– E.g., antennas
• There is no chip until the router is done
• Must / Should / Can tomorrow’s IC routers
“independently” address these issues?
http://vlsicad.ucsd.edu
ICCAD 2003
Whose Job Is It To Solve:
• Mask NRE cost ( runtimes  shapes complexity)
• BEOL catastrophic yield loss
– Deposited copper  can infer yield loss mechanisms
• Open faults more prevalent than short or bridging faults
• High-resistance via faults
• Cf. “non-tree routing” for reliability and yield?
– Variability budget for planarization
• Copper is soft  dual-material polish mechanisms
• Oxide erosion and copper dishing  cross-sectional
variability, inter-layer bridging faults, …
• Low-k: thermal properties, anisotropy, nonuniformity
• Resistivity at small conductor dimensions
http://vlsicad.ucsd.edu
ICCAD 2003
The Problem: Evolution
• Conflicting goals
– Designer: “freedom”, “reuse”, “migration”
– EDA: “maintenance mode”
– Process/foundry: “enhance perceived value”
(= add rules)
–  Prisoner’s Dilemma: who will invest in change?
• Fiddling: Incremental, linear extrapolation of
current trajectory
– “GDS-3”
– Thin post-processing layers (decompaction, RET
insertion, …)
– Leads to “dark future” (12th Japan DA Show keynote)
http://vlsicad.ucsd.edu
ICCAD 2003
DAC-2003 Nanometer Futures Panel:
Where should extra R&D $ be spent?
Variability/Litho/Mask/Fab
Power Delivery/Integrity
Low Power/Leakage
Tool/Flow Enhancements/OA
IP Reuse/Abstraction/SysLevel Design
P&R and Opt
DSM Analysis
Others (Lotto)
100%
80%
60%
40%
20%
0%
Intel
http://vlsicad.ucsd.edu
IBM
Synopsys
TUEMagma
Cadence
STMicro
ICCAD 2003
The Solution: Co-Evolution
• Designer, EDA, and process communities cooperate
and co-evolve to maintain the cost (value) trajectory
of Moore’s Law
– Must escape Prisoner’s Dilemma
– Must be financially viable
– At 90nm to 65nm transition, this is a matter of survival for
the worldwide semiconductor industry
http://vlsicad.ucsd.edu
ICCAD 2003
Today’s Design-Manufacturing Interfaces
Litho/Process
(Tech. Development)
Design Rules
Device Models
Library
(Library Team)
Layout & libs
(Corner Case
Timing)
RET
Mask: Dataprep
(Mask House)
Design
Layout
(collection of polygons ?)
(ASIC Chip)
Tapeout
Guardbanding all the way in all stages!!
(e.g. clock ACLV guardband ~ 30%)
What do we lose ?
• Performance  Too much worst-casing
• Turnaround time  Huge OPC runtimes, overdesign
• Predictability  RET is applied post-design
• Mask costs  Overcorrection
• Designer’s intent  RET is not driven by design
http://vlsicad.ucsd.edu
ICCAD 2003
Foundation of the DFM Solution
• Bidirectional design-manufacturing data pipe
– Fundamental drivers: cost, value
• Pass functional intent to manufacturing flow
– Example: RET for predictable timing slack, leakage, yield
– RETs should win $$$, reduce performance variation
–  cost-driven, parametric yield constrained RET
• Pass limits of manufacturing flow up to design
– Example: avoid corrections that cannot be manufactured
or verified  e.g., design should be aware of metrology
N.B.: 1998-2003 papers/tutorials: http://vlsicad.ucsd.edu/~abk/TALKS/
http://vlsicad.ucsd.edu
ICCAD 2003
This Tutorial
•
•
•
•
•
•
•
•
Concrete examples of Manufacturing-Driven PD
Deployable today
Topic 1: Composability: PSM and SRAF
Topic 2: Performance impact limited fill insertion
Topic 3: Function Aware OPC
Topic 4: Library-based OPC for predictability
Topic 5: Focus and proximity-effects aware STA
Some ramblings about future: regular layout, robust
optimization, leakage saving without multi-Vt
• We will start with a “manufacturing primer” …
http://vlsicad.ucsd.edu
ICCAD 2003
Outline
• Challenges
• “DFM Philosophy”
• Manufacturing and Variability Primer
– Lithography, Masks and Process Variations
•
•
•
•
•
•
Design for Value
Composability
Performance Impact Limited Fill Insertion
Function Aware OPC
Systematic Variation Aware STA
Futures of Mfg-Aware PD
http://vlsicad.ucsd.edu
ICCAD 2003
Photo-Lithographic Process
optical
mask
oxidation
photoresist
removal (ashing)
photoresist coating
stepper exposure
Typical operations in a single
photolithographic cycle (from [Fullman]).
photoresist
development
acid etch
process
step
http://vlsicad.ucsd.edu
spin, rinse, dry
ICCAD 2003
Lithography Primer: Basics
• The famous Raleigh Equation:
: Wavelength of the exposure system
NA: Numerical Aperture (sine of the capture angle of the
lens, and is a measure of the size of the lens system)
k1: process dependent adjustment factor
• Exposure = the amount of light or other radiant energy
received per unit area of sensitized material.
• Depth of Focus (DOF) = a deviation from a defined
reference plane wherein the required resolution for
photolithography is still achievable.
• Process Window = Exposure Latitude vs. DOF plot for
given CD tolerance
http://vlsicad.ucsd.edu
ICCAD 2003
Numerical Aperture
•NA=nsin  n=refractive index  for air, UB =1. Practical limit ≈ 0.93
•NA increase  DOF decrease
•Immersion lithography ?  n>1 (e.g., water)
http://vlsicad.ucsd.edu
Figures courtesy www.icknowledge.com
ICCAD 2003
k1
•k1 is complex process depending on RET techniques,
photoresist performance, etc
•Practical lower limit ≈ 0.25
•Minimum resolvable dimension with 193nm steppers =
0.25*193/0.93 = 52nm
http://vlsicad.ucsd.edu
Source: www.icknowledge.com
ICCAD 2003
RET Basics
4
• The light interacting with the mask is a wave
3
B
• Any wave has certain fundamental
properties
–
–
–
–
2
Wavelength ()
1
Direction
0Amplitude
Amplitude
Phase
-1

Direction
Phase
-2
• RET is wavefront-3 engineering
to enhance lithography
-4
by controlling these
properties
-20
0
20
40
60
80
100
Courtesy F. Schellenberg, Mentor Graphics Corp.
http://vlsicad.ucsd.edu
ICCAD 2003
Direction: Illumination
• Regular Illumination
• Many off-axis designs (OAI)
– Annular
– Quadrupole / Quasar
– Dipole
http://vlsicad.ucsd.edu
or
+
ICCAD 2003
OAI: Impact on PD
• Prints only one orientation
• Must decompose layout
for 2 exposures
http://vlsicad.ucsd.edu
130 nm lines, printed
at different pitches
Quasar illumination
NA=0.7
1
0.5
Acceptable
Unacceptable
Pitch
(nm)
0
200
400
600
800
Isolated
– Dipole Illumination
1.5
Dense
• Amplifies dense 0°, 90 °
lines
• Destroys ±45° lines
Without SRAF
Depth of Focus
• Off axis amplifies certain
pitches at the expense of
the others “Forbidden”
pitches
– Quasar / Quadrupole
Illumination
1000
1200
1400
Graph reference: Socha et al. “Forbidden Pitches for 130 nm
lithography and below”,
in Optical Microlithography XIII, Proc. SPIE Vol. 4000 (2000),
1140-1155.
ICCAD 2003
Amplitude: OPC
• Optical Proximity
Correction (OPC)
modifies layout to
compensate for
process distortions
– Add non-electrical
structures to layout
to control
diffraction of light
– Rule-based or
model-based
http://vlsicad.ucsd.edu
ICCAD 2003
OPC: Assist Features
Exposure
Dense CD
window
Iso CD
window
Process Overlap Window
Iso-window after SRAF insertion
Defocus
• SRAF = Sub-Resolution Assist Feature
≡ SB = Scattering Bar ≡ Assists
• SRAFs make isolated lines “behave” as dense
• SRAF are not supposed to be printed on wafer but exist on
mask
http://vlsicad.ucsd.edu
ICCAD 2003
Phase: PSM
• Phase Shifting Masks (PSM) etch
topography into mask
– Creates interference fringes on the wafer
Interference effects boost contrast Phase
Masks can make extremely small gates
conventional mask
glass
phase shifting mask
Chrome
Phase shifter
Electric field at mask
Intensity at wafer
http://vlsicad.ucsd.edu
ICCAD 2003
Double-Exposure Bright-Field PSM
0
180
180
http://vlsicad.ucsd.edu
+
=
ICCAD 2003
The Phase Assignment Problem
• Assign 0, 180 phase regions such that critical
features with width < B are induced by adjacent
phase regions with opposite phases
shifters
0
180
<B
http://vlsicad.ucsd.edu
ICCAD 2003
Key: Global 2-Colorability
• Odd cycle of “phase implications”  layout
cannot be manufactured
– layout verification becomes a global, not local, issue
180
http://vlsicad.ucsd.edu
0
?
180
180
0
180
ICCAD 2003
Phase Assignment for Bright-Field PSM
• PROPER Phase Assignment:
–Opposite phases for opposite shifters
–Same phase for overlapping shifters
http://vlsicad.ucsd.edu
Overlapping shifters
ICCAD 2003
Critical features:
F1,F2,F3,F4
F2
F1
F4
F3
http://vlsicad.ucsd.edu
ICCAD 2003
F2
F1
Opposite-Phase
Shifters (0,180)
http://vlsicad.ucsd.edu
F4
F3
ICCAD 2003
S3
F2
S4
S1
F1
S8
F4
S7
S2
S5
F3
S6
Shifters: S1-S8
PROPER Phase Assignment:
– Opposite phases for opposite shifters
– Same phase for overlapping shifters
http://vlsicad.ucsd.edu
ICCAD 2003
Phase Conflict
S3
F2
S4
S1
F1
S8
F4
S7
S2
S5
F3
S6
Phase Conflict
Proper Phase Assignment is IMPOSSIBLE
http://vlsicad.ucsd.edu
ICCAD 2003
Conflict Resolution: Shifting
S3
F2
S4
S1
F1
S8
F4
S7
S2
Phase Conflict
http://vlsicad.ucsd.edu
S5
F3
S6
feature shifting
to remove overlap
ICCAD 2003
Conflict Resolution: Widening
S3
F2
S4
S1
F1
S8
F4
S7
S2
F3
Phase Conflict
feature widening to turn
conflict into non-conflict
http://vlsicad.ucsd.edu
ICCAD 2003
Minimum Perturbation
Problem
• Layout modifications
–feature shifting
–feature widening
 area increase, slowing down
 manual fixing, design cost increase
• Minimum Perturbation Problem: Find min #
of layout modifications leading to proper
phase assignment. [Kahng et al. ASPDAC 2001]
http://vlsicad.ucsd.edu
ICCAD 2003
Mask Costs(1)
OPC
Design
Fracture
Mask
Mask Cost  Data Volume
OPC, PSM, Fill  increased feature complexity
 increased mask cost
Figure courtesy Synopsys Inc.
http://vlsicad.ucsd.edu
ICCAD 2003
Mask Costs(2)
Half of all mask sets
used for < 570 wafers
(< 100K parts)
Others
Materials
Vector scan: Write cost
proportional to feature
complexity
Difficult to inspect, verify
masks!
http://vlsicad.ucsd.edu
Data Prep.-OPC conversion/e-beam file
Defect Repair
Defect Inspection
Writing-Optical or e-beam
0
10
20
30
Weight in Mask Cost (%)
ICCAD 2003
40
Manufacturing Yield
• IC manufacturing process affected by
random disturbances
– different silicon dioxide growth rates, mask
misalignment, drift of
fabrication equipment operation, etc….
– These disturbances are often uncontrollable and affect
the circuit performance
• Yield: percentage of manufactured products that
pass all performance specifications
– Parametric yield (process variations)
• What is the performance of the manufactured chips?
– Catastrophic or functional yield (defects)
• How many chips work?
http://vlsicad.ucsd.edu
ICCAD 2003
Process Variation Taxonomy
• Spatial scale:
– Die-to-Die or Inter-Die. E.g.
Focus, etch
– Within-Die or Intra-Die. E.g.
lens aberration, diffraction
effects
• Nature:
– Random. E.g. batch-to-match
material variation
– Systematic. E.g. diffractionbased proximity effects
– Systematic but difficult to
model variations  random
http://vlsicad.ucsd.edu
ICCAD 2003
Process Variation Sources
• Wafer: topography, reflectivity
• Reticle: CD error, proximity effects, defects
• Stepper: Lens heating, focus, dose, lens
aberrations
• Etch: Power, pressure, flow rate
• Resist: Thickness, refractive index
• Develop: Time, temperature, rinse
• Environment: Humidity, pressure
http://vlsicad.ucsd.edu
ICCAD 2003
Simulation of Variation
• Value X for a given parameter for a device i in
path j in the kth Monte-Carlo run is given by
–
–
–
–
RAN-WID: Random within-die variation
RAN-DTD: Random die-to-die variation
SYS-WID: Systematic within-die variation
SYS-DTD can not be accounted for at die-scale
http://vlsicad.ucsd.edu
ICCAD 2003
Simulation of Variation (2)
Systematic effects
should be correctly
accounted for.
Treating them as
random is an
oversimplification
• (, ) for various components should be
correctly reconstructed depending on their
initial decomposition at the litho stage
http://vlsicad.ucsd.edu
ICCAD 2003
die/MC sims 
“Ideal” Sampling ?
• RowWID
– row = WID
• ColumnDTD
– col = DTD
x11
x1n
xm1
xmn
Devices on a die 
s
• Systematic variation, correlationsfurther
dependence within rows and columns
• Can such a multi-variate distribution be sampled? Is
it even feasible ?
• What is the relation between  of various
components in this case ?
http://vlsicad.ucsd.edu
ICCAD 2003
Distributions: Gaussian ??
• Etch variation is radial
– Less die at center than periphery  CD variation
due to etch is asymmetric
• Focus based CD variation
– Behavior of Isolated and
dense lines systematically
different  pattern dependent
variation
– Post-SRAF insertion, CD
distribution biased towards
dense lines  asymmetry
– More on this later..
http://vlsicad.ucsd.edu
ICCAD 2003
Outline
•
•
•
•
•
•
•
•
•
Challenges
“DFM Philosophy”
Manufacturing and Variability Primer
Design for Value
Composability
Performance Impact Limited Fill Insertion
Function Aware OPC
Systematic Variation Aware STA
Futures of Mfg-Aware PD
http://vlsicad.ucsd.edu
ICCAD 2003
Mapping Design to Value: Selling Points
AMD Processors
Athlon MP
450
Athlon 4 Mobile
400
Athlon Desktop
Price ($)
350
Duron
300
Duron Mobile
250
200
150
100
50
0
0
200
400
600
800
1000
1200
1400
Clock Speed (MHz)
http://vlsicad.ucsd.edu
ICCAD 2003
1600
Design for Value (DFV)*
•
Mask cost trend  Design for Value (DFV)
Design for Value Problem:
Given
•
•
•
•
Performance measure f
Value function v(f)
Selling points fi corresponding to various values of f
Yield function y(f)
Maximize Total Design Value = i y(fi)*v(fi)
[or, Minimize Total Cost]
•
Probabilistic optimization regime
* See "Design Sensitivities to Variability: Extrapolation and Assessments in Nanometer VLSI",
IEEE ASIC/SoC Conference, September 2002, pp. 411-415.
http://vlsicad.ucsd.edu
ICCAD 2003
DFV vs. Design for Performance
(DFP)
• DFP:
– T = circuit delay
– yi = process parameters
– xi = design parameters
• DFV:
– Tm = Selling point delay
– PT = Cumulative probability (yield)
http://vlsicad.ucsd.edu
ICCAD 2003
Example: Repeater Insertion
• 130nm single
repeatered 5mm
global line with ITRS
based Leff variation
considered
• Repeater location is
varied
• DFP: nominal delay
optimized
• DFV: Yield at given
threshold delay
optimized
http://vlsicad.ucsd.edu
DFV and DFP
optima are different
ICCAD 2003
Post-Opt
#Paths
DFV: Impact of #critical paths
Timing slack
• DFP optimizationA “wall” of optimized
critical pathsincrease in expected
circuit delay in presence of variation
• Intentional “under-optimization” ? E.g.,
[IBM DAC’02]
http://vlsicad.ucsd.edu
ICCAD 2003
Statistical Static Timing
• Important component of DFV is a
statistical static timing analysis (SSTA)
• Simplest SSTA: Monte-Carlo STA
– Sample process parameters from their
distributions
– Generate a delay value for every timing arc
– Update SDF and run standard STA
– Repeat statistically significant no. of times
and generate a circuit delay distribution
http://vlsicad.ucsd.edu
ICCAD 2003
SSTA: Other Approaches
• Problem is to compute distribution of
maximum of random variables
– Intelligent Monte-Carlo [UCSB DAC’02]
– Bound-based [UCB DAC’02], [IBM DAC’03],
[UMich TAU’02]
• Problems with current approaches:
–
–
–
–
Runtime, scalability
Ability to handle correlations
Ability to handle non-Gaussian distributions
Incremental SSTA ?
http://vlsicad.ucsd.edu
ICCAD 2003
Outline
•
•
•
•
•
Challenges
“DFM Philosophy”
Manufacturing and Variability Primer
Design for Value
Composability
– PSM and Assists
•
•
•
•
Performance Impact Limited Fill Insertion
Function Aware OPC
Systematic Variation Aware STA
Futures of Mfg-Aware PD
http://vlsicad.ucsd.edu
ICCAD 2003
Conflict Graph for Cell-Based Layouts
• Coarse view: at level of connected components of
conflict graphs within each cell master
• each of these components is independently phase-assignable
• can be treated as a single “vertex” in coarse-grain conflict graph
cell master A
cell master B
connected component
edge in coarse-grain conflict graph
http://vlsicad.ucsd.edu
ICCAD 2003
Standard-Cell PSM
• Must: Free composability of standard cells
– Exit placer with a phase-shiftable layout
– No loops back into the placer
• RETs may interfere: unique master cell with
only one instantiation causes area loss
• Can exploit:
– Multiple phase-shifted versions of master cell
–Version-composability matrix
http://vlsicad.ucsd.edu
ICCAD 2003
Taxonomy of Composability
• (Same) Same row composability: any cell can be
placed immediately adjacent to any other
• (Adj) Adjacent row composability: any two cells
from adjacent rows are freely combined
• Four cases of cell libraries
G = guaranteed composability
NG = non-guaranteed composability
– Adj-G/Same-G  free composability
– Adj-G/Same-NG  less free
– Adj-NG/Same-G  painful
– Adj-NG/Same-NG  non-starter…
http://vlsicad.ucsd.edu
ICCAD 2003
Taxonomy of Composability
VDD
GND
Adj-G/Same-NG
VDD
VDD
GND
Adj-NG/Same-G
VDD
VDD
GND
Adj-NG/Same-NG
VDD
http://vlsicad.ucsd.edu
ICCAD 2003
Adj-G/Same-NG: Versioning
GIVEN:
order of cells in a row
version compatibility matrix
FIND: version assignment such that versions
of adjacent cells are compatible
• (BFS) traversal of DAG
– nodes = versions
– arcs = compatibility
http://vlsicad.ucsd.edu
ICCAD 2003
Adj-G/Same-NG: Shifting
GIVEN:
- order of cells in a row (or “optimal” placement)
- version compatibility weighted matrix
(weight = #extra sites)
FIND: version assignment minimizing either
total # of extra sites or total/max displacement
from optimal placement
• Dynamic Programming O(kV)
k = max displacement
http://vlsicad.ucsd.edu
ICCAD 2003
Assist Features and Variation
SB = Scattering Bar  SRAF
0.22
0.2
0.18
CD
0.16
0.14
0.12
0.1
0.08
2 SB
1 SB
W/O SB
0.06
DOF
0.04
• SRAFs are dummy geometries
– Improve process window
overlap for dense and isolated
features
– Not supposed to be printed
– Unavoidable for 90nm poly
http://vlsicad.ucsd.edu
0.0
0.1
SB2
0.2
0.3
SB1
0.4
0.5
0.6
No SB
ICCAD 2003
Layout Composability for SRAFs
Better than
x+dx
x
• Feature spacings are restricted to a small set
• Two components
– Assist-correct library layouts  Inter-device
spacing within a standard cells  Intelligent library
design
– Assist-correct placement  space between cells
needs to be adjusted  Intelligent whitespace
management
http://vlsicad.ucsd.edu
ICCAD 2003
Assist-Correct Placement
s1
s3
(s1+s3+ws)2 Assist-Corr.-set
ws
(s2+s4+ws)2 Assist-Corr.-set
s2
s4
• Change whitespace distribution to make the
placement assist-correct
• Can be formulated and solved as a postplacement minimum perturbation problem
• Does not work well with cell layouts having
non-preferred direction critical poly
http://vlsicad.ucsd.edu
ICCAD 2003
Outline
•
•
•
•
•
•
•
•
•
Challenges
“DFM Philosophy”
Manufacturing and Variability Primer
Design for Value
Composability
Performance Impact Limited Fill Insertion
Function Aware OPC
Systematic Variation Aware STA
Futures of Mfg-Aware PD
http://vlsicad.ucsd.edu
ICCAD 2003
CMP & Area Fill
Chemical-Mechanical Planarization (CMP)
Polishing pad wear, slurry composition, pad elasticity make this a
very difficult process step
wafer carrier
silicon wafer
polishing pad
slurry feeder
slurry
polishing table
Area fill feature insertion
Decreases local density variation
Decreases the ILD thickness variation after CMP
Features
Post-CMP ILD thickness
Area fill
features
http://vlsicad.ucsd.edu
ICCAD 2003
Fixed-Dissection Regime
• To make filling more tractable, monitor only fixed set of
w  w windows
– offset = w/r (example shown: w = 4, r = 4)
• Partition n x n layout into nr/w  nr/w fixed dissections
• Each w  w window is partitioned into r2 tiles
w
w/r
tile
Overlapping
windows
n
http://vlsicad.ucsd.edu
ICCAD 2003
Density Control Objectives
Objective for Manufacture = Min-Var [Kahng et al., TCAD’02]
minimize window density variation
subject to upper bound on window density
Objective for Design = Min-Fill [Wong et al, DAC’00]
minimize total amount of added fill
subject to UB on window density variation
http://vlsicad.ucsd.edu
ICCAD 2003
Performance-Impact
Limited Area Fill (PIL Fill)
• Why?
Filled layout
– Fill features insertion  increased
capacitance increased
interconnect delay and crosstalk
– Post-tapeout fill synthesis 
Incorrect timing closure ?
General guidelines:
• Minimize total number of fill features
• Minimize fill feature size
• Maximize space between fill features
• Maximize buffer distance between original and fill
features
http://vlsicad.ucsd.edu
ICCAD 2003
PIL Fill Formulation
Given
• A fixed-dissection routed layout
• Design rule for floating square fill features
• Prescribed amount of fills in each tile
Fill layout with the following objective:
Max-MinSlack-Fill-Constrained (MSFC) :
Maximize minimum post-fill slack over all nets,
subject to layout density constraints
[Chen et al, DAC’03]
http://vlsicad.ucsd.edu
ICCAD 2003
Capacitance and Delay Models
• Interconnect capacitance = Overlap + Coupling + Fringe
• Fringe, Overlap require cognizance of multiple layers
 Consider fill impact on coupling capacitance only
• Elmore delay model  incremental additivity of delay with
added parasitic capacitance
Active
lines
top view
w
fill grid
pitch
buffer distance
http://vlsicad.ucsd.edu
– Capacitance between two
active lines separated by
distance d, with m fill features
in one column:
Cap 
0 r  a
d  mw
ICCAD 2003
Iterated MSFC Fill Approach
1. Run STA and sort fill columns in decreasing order
of timing slack
2. Greedily insert fill into columns till
1. Fill requirement of tile is met; or
2. No column with slack > LB remains; or
3. Total added delay due to fill > UB
3. Decrease LB, UB. Update parasitics.
4. If fill requirement of tile is not met, goto 1
5. Pick next tile to be filled. Goto 1
UB, LB are iteration variables to control accuracy vs. STA
iterations tradeoff. More details in [Chen et al, DAC’03]
http://vlsicad.ucsd.edu
ICCAD 2003
Experiments for MSFC PIL-Fill
Iterated Greedy Approaches for MSFC PIL-Fill
2500
M i n i m u m S l a c k (ps)
2000
1500
1000
Orig MinSlack
Normal MinSlack
MSFC MinSlack
500
0
1
2
3
4
5
6
-500
-1000
Testcases
Normal fill flow  LP/Monte-Carlo (TCAD’02)
http://vlsicad.ucsd.edu
ICCAD 2003
Outline
•
•
•
•
•
•
•
Challenges
“DFM Philosophy”
Manufacturing and Variability Primer
Design for Value
Composability
Performance Impact Limited Fill Insertion
Function Aware OPC
– Minimizing cost of corrections
– Library-based correction
• Systematic Variation Aware STA
• Futures of Mfg-Aware PD
http://vlsicad.ucsd.edu
ICCAD 2003
DFV at Process Level: FunctionAware OPC
• Annotate features with “required amount” of OPC
– E.g., why correct dummy fill?
– Determined by design properties such as setup and hold
timing slacks, parametric yield criticality of devices and
features
• Reduce total OPC inserted (e.g., SRAF usage)
– Decreased physical verification runtime, data volume
– Decreased mask cost resulting from fewer features
• Supported in data formats (OASIS, IBM GL-I,
OA/UDM)
– Design through mask tools need to make, use annotations
• N.B.: General RET trajectory: rules  models 
libraries
http://vlsicad.ucsd.edu
ICCAD 2003
DFV in OPC Regime
Given: Admissible levels of (OPC) correction for each
layout feature, and corresponding delay
impact (mean and variance)
Find: Level of correction for each layout feature,
such that a prescribed selling point delay is
attained
Objective: Minimize total cost of corrections
http://vlsicad.ucsd.edu
ICCAD 2003
•
Variation-Aware Library
Models
Each capacitance or delay value replaced by (,)
pair
• Variation aware .lib
pin(A) {
direction : input;
capacitance : (0.002361,0.0003) ;
}
…
timing() {
related_pin : "A";
timing_sense : positive_unate;
cell_rise(delay_template_7x7) {
index_1 ("0.028, 0.044, 0.076");
index_2 ("0.00158, 0.004108, 0.00948");
values ( \
“(0.04918,0.001), (0.05482,0.0015), (0.06499,0.002)",
….
http://vlsicad.ucsd.edu
ICCAD 2003
Correction = Mask Cost = CD Control
•
Levels of RET = Levels of CD control
Type
of OPCof Ldrawn
3 of
• Levels
RET =
levels of CD(nm)
control Ldrawn
Figure
Count
Delay (, ) for
NAND2X1
Aggressive
130
5%
5X
(64.82, 2.14)
Medium
130
6.5%
4X
(64.82, 2.80)
No OPC
130
10%
1X
(64.82, 4.33)
CD studies due to D. Pramanik,
Numerical Technologies, December 2002
http://vlsicad.ucsd.edu
OPC solutions due to K. Wampler,
MaskTools, March 2003
ICCAD 2003
Generic SSTA-Based Cost of
Correction Methodology
Nominally Correct
SP&R Netlist
SSTA
Yield
Target met
?
N
Correction
Algorithm
SSTA
http://vlsicad.ucsd.edu
• Statistical STA (SSTA)
provides PDFs of arrival
Min. Corrected
Library
times at all nodes
• Assume variation aware
library models (for delay)
Y
EXIT
are available
• Statistical STA currently
has runtime and scalability
All Correction
Libraries
issues
All Correction
Libraries
ICCAD 2003
MinCorr: Parallels to Gate Sizing
• Assume
– Gaussian-ness of distributions prevails
  + 3 corresponds to 99% yield
– Perfect correlation of variation along all paths
 Die-to-Die variation
 1+2 + 31+2 = 1 + 31 + 2 + 32
• Resulting linearity allows propagation of (+3) or
99% (selling point) delay to primary outputs using
standard Static Timing Analysis (STA) tools
• (See DAC-2003 paper)
http://vlsicad.ucsd.edu
ICCAD 2003
MinCorr: Parallels to Gate Sizing
MinCorr
Gate Sizing Problem:
delay (+k)
costs of correction
Given allowed areas and corresponding delays of each cell,
minimize total die area subject to a cycle time constraint
selling point delay
cost of OPC
Gate Sizing

MinCorr
Cell Area

Cost of correction
Nominal Delay

Delay (+k)
Cycle Time

Selling point delay
Die Area

Total cost of OPC
http://vlsicad.ucsd.edu
ICCAD 2003
MinCorr Methodology (DAC-03)
• Mapping of area minimization to RET cost optimization
• “Yield library” analogous to timing libraries (e.g., .lib)
• Synthesis tool (Design Compiler) performs “gate
sizing”
– Figure counts, critical dimension (CD) variations derived
from Numerical Technologies OPC tool*
– Restricted TSMC 0.13 m library (7 cell masters: BUF, INV,
NAND, NOR)
– Approach tested on small combinational circuits
• alu128: 8064 cells
• c7552: 2081 cell ISCAS85 circuit
• c6288: 2769 cell ISCAS85 circuit
• Up to 79% reduction in figure complexity without any
parametric yield impact
http://vlsicad.ucsd.edu
ICCAD 2003
OPC and Designer’s Intent
• OPC applied post-tapeout
– Overcorrection (matching corners)  mask
cost
– Large runtimes
– Impact of OPC on performance unknown
• Designer’s intent: OPC quality metrics
– CD (Poly over active)
• Non-critical poly need
not be well-controlled
– Contact Coverage
• “Perfect” corners unnecessary
if there is enough contact overlap
http://vlsicad.ucsd.edu
ICCAD 2003
•
Example Caution: OPCing
OPC
Historical rule on line end extension
Truly desired on wafer
Layout according to design rule
• OPC software assumes the layout is the target, and adds
OPC to the old OPC extension
OPC on the OPC
• With model-based OPC, design rules can be much more
aggressive
http://vlsicad.ucsd.edu
Figures courtesy F. Schellenberg, Mentor Graphics
ICCAD Corp.
2003
CD Error Distribution
•Library based correction shows highly accurate average CD
http://vlsicad.ucsd.edu
ICCAD 2003
Systematic ACLV
• ACLV = Through-pitch variation (50%) + Topography
variation (10%) + Mask variation + Etch, residuals
• Current timing analysis (statistical or deterministic STA)
assumes all variation is ‘random’
• 50% of ACLV can be predictable by analyzing the layout
“Smile-frown” plots indicate:
1. Through focus variation is
systematic
2. Corners for timing analysis are
derived from worst-case ACLV
tolerance  instance specific
tolerances are much tighter
http://vlsicad.ucsd.edu
Figure courtesy ASML MaskTools
ICCAD 2003
Taming Pattern and Focus
Variation
1.
2.
3.
Obtain a set of nominal CD (wafer image simulation) for
typical environments of the cell in a chip  environment
specific timing libs (typical ASIC libs very limited set of
environments)
Run in-context STA (post-placement) with context-specific
timing libs  accurate nominal timing at zero focus
condition
Input to output delay modeling based on the iso-ness and
dense-ness of transistors in the input to output paths 
more accurate delay variation analysis in STA
http://vlsicad.ucsd.edu
Work done at IBM
ICCAD 2003
Taming..: Timing Results
Traditional Timing
New “Accurate” Timing
Testcase
NOM
BC
WC
NOM
BC
WC
C1355
C2670
C3540
C432
C499
2.15
5.07
6.32
5.77
2.30
1.57
3.74
4.72
4.21
1.66
2.88
6.64
8.34
7.70
3.10
2.15
5.05
6.26
5.70
2.29
1.70
4.04
5.20
4.53
1.79
2.62
5.96
7.35
6.88
2.82
http://vlsicad.ucsd.edu
Work done at IBM
ICCAD 2003
Outline
•
•
•
•
•
•
•
•
•
Challenges
“DFM Philosophy”
Manufacturing and Variability Primer
Design for Value
Composability
Performance Impact Limited Fill Insertion
Function Aware OPC
Systematic Variation Aware STA
Futures of Mfg-Aware PD
– RDR’s, robust optimization, leakage
http://vlsicad.ucsd.edu
ICCAD 2003
Acknowledgements
•
•
•
The Library-Based OPC and Systematic ACLV based STA work is still
unpublished and was done at IBM during Puneet Gupta’s summer
internship. We would like to thank Fook-Luen Heng, Daniel Ostapko, Mark
Lavin, Ronald Gordon, Kafai Lai and all our collaborators in the work.
Dennis Sylvester and Jie Yang at University of Michigan were our
collaborators for the MinCorr and variability-impact projection work. Yu
Chen (Ubitech) was the coauthor for our work on PIL-Fill.
We would also like to thank Frank Schellenberg (Mentor Graphics Corp.),
Tim Yao Wong (CMU) and Dennis Sylvester for letting us use parts of their
previous talks.
http://vlsicad.ucsd.edu
ICCAD 2003
Notes on Regular Layout
• 65 nm has high likelihood for layouts to look like
regular gratings
– Uniform pitch and width on metal as well as poly layers
–  Predictable layouts even in presence of focus and dose
variations
• More manufacturable cell libraries with regular
structures
• New layout challenges (e.g., preserving regularity in
placement)
http://vlsicad.ucsd.edu
ICCAD 2003
Regular Layouts
• Standard cells
– high performance, high density, low part cost, low
power
– escalating NRE, TAT, variability
• Programmable devices (FPGA)
– regular, predictable, fast TAT, low NRE
– low performance, low density, high part cost, high
power
• Middle ground: e.g. via programmability (eASIC,
CMU)
– VPGA – retain regularity, but remove field
programmability
– Use only a few via masks to configure a circuit
* Courtesy Center for Silicon System Implementation, CMU.
http://vlsicad.ucsd.edu
ICCAD 2003
Via Patterning
Connection
not made
Connection
made
Sample synthesis Results
Design
Area (μm2)
Delay(ns)
ALU (ASIC)
5600
0.950
ALU (VPGA-Lib)
7800
0.802
ALU (CLB Array)
18225
0.808
DLX (ASIC)
5476
1.505
DLX (VPGA-Lib)
9216
1.442
DLX (CLB Array)
16875
1.461
* Courtesy Center for Silicon System Implementation, CMU.
http://vlsicad.ucsd.edu
ICCAD 2003
Stochastic/Robust Optimizations
• Physical design is no longer deterministic
• An example “probabilistic” LP:
• Problem: Too slow and not at all scalable
http://vlsicad.ucsd.edu
ICCAD 2003
Example: Robustness Metric
for Power Distribution
• Power distribution analysis by solving GV=I
– G = Conductance matrix of the power distribution
network
– I = Current requirements for sinks
– V = IR drop (if Vdd is put to 0)
– ||V|| = Peak IR drop (l-1 norm)
• Random variations
– G : E.g., width and thickness variation
– I : E.g., inaccurate estimation of peak currents
http://vlsicad.ucsd.edu
ICCAD 2003
Example: Robustness Metric
for Power Distribution (2)
• Perturbation analysis:
– E = random perturbation in G
– e = random perturbation in I
– V’ = IR drop map after perturbation
• ||G||||G-1|| = condition number =
measure of robustness
http://vlsicad.ucsd.edu
ICCAD 2003
Leakage: Understanding + Control
• Understanding: variation in
chip-level leakage due to
intra- and inter-die Leff
variation
 cost-benefit of controlling
relevant variation sources
• Control: Multi-everything
(threshold, supply, sizing)
http://vlsicad.ucsd.edu
ICCAD 2003
Multi-Lgate Design for Leakage?
Leakage
Delay
1.80E-07
8.00E-11
1.60E-07
7.00E-11
1.40E-07
6.00E-11
1.20E-07
5.00E-11
1.00E-07
4.00E-11
Lgate
0.15
0.15
0.14
0.14
0.14
0.13
0.13
0.13
0.12
0.12
0.12
0.12
0.11
0.11
0.1
0.11
0.15
0.15
0.14
0.14
0.14
0.13
0.13
0.13
0.12
0.12
0.12
0.12
0.11
0.00E+00
0.11
0.00E+00
0.1
2.00E-08
0.11
4.00E-08
1.00E-11
0.1
6.00E-08
2.00E-11
0.1
8.00E-08
3.00E-11
Lgate
• Lgate biasing from 130nm to 140nm
• Leakage benefit = 29%
• Delay overhead = 5% ; Dynamic power overhead = 3.5%
• Potential alternative/supplement to multi-Vt design
• Avoid high variability in low Vt and manufacturing overheads of multi-Vt
• CD variability (as a %) is less for larger Lgate design
http://vlsicad.ucsd.edu
ICCAD 2003
Conclusions
• Designer, physical design, and mask communities
must maintain cost (value) trajectory of Moore’s Law
– Wakeup call: Intel 157nm announcement
• Bidirectional design-mfg data pipe driven by cost,
value
– Pass functional intent to mask and foundry flows
– Pass limits of mask and foundry flows up to design
• Examples
–
–
–
–
–
Manufacturability and cost/value optimization
Exploitation of systematic variations (e.g., iso-dense)
Composability
Performance impact-limited dummy fill
Intelligent mask data prep, restricted design rules, etc.
• Manufacturing-aware PD: much work lies ahead
http://vlsicad.ucsd.edu
ICCAD 2003
http://vlsicad.ucsd.edu
ICCAD 2003