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Meeting Agenda Introduction (9:00-9:30) Application driver focus of the GSRC, and implications for C.A.D. Theme C.A.D. Theme status and futures GTX (Technology Extrapolation) Tool status and current development (Mike Oliver) (9:30-9:45) Recent work (9:45-10:45) DRAM (Michael Wang (Dai)) Interconnect modeling (Xuejue Huang (King)) Global signaling (Himanshu Kaul (Sylvester)) What can GTX do to support drivers? (10:45-11:30) Bookshelf (CAD-IP Reuse) Status and summary of recent work (Igor Markov) (11:30-noon) Open Access (1:00-2:00) What can Bookshelf do to support drivers = vertical benchmarks++ ? (2:00-2:45) Roadmap for C.A.D. Theme + action items (until adjourn) 1 C.A.D. Initiatives Specification Gap: e.g., What will be the critical design problem? GTX GTX models include canned optimizations = canned design space explorations Development and Delivery Gap: e.g., How to deploy DT better/faster? Bookshelf Measurement Gap: e.g., Did achievable design improve? Metrics Definition of success (Next up: Education? Measuring research process?) Shared Context Is A Force Multiplier 2 Ubiquitous Node Design Specifications Major Constraints (depending upon the application) Cost: < 1 $ Size: 1 mm3 … 1 cm3 Power: between 10 mW and 100 mW (depending upon ubiquitousness and mobility) Hybrid Mixed-signal (sensing, air interface, power train) Mixed technology (passives, MEMs) Limited flexibility Downloadable and adaptable application layer Parameterizable interfaces 3 Perspective: Single-Chip Bluetooth Radio (Alcatel, 2001) 4 PicoNode V3 Architecture SIF = sensor interface 16kB CODE 4kB XDATA 256 DATA Chip Supervisor DW8051 Flash Storage Serial sfrbus or membus? 20MHz Clock Source FlashIF SIF ADC MAC Voltage Voltage Supply Voltage Supply Supply SIF LocalHW Serial GPIO ADC PHY Sensor1 Sensor2 PrgThresh0 PrgThresh1 User Interface OOK Receiver Tx0 Tx2 OOK Transmitter 5 Challenge: Packaging “Smart Dust” mote Combines sensing, computation, optical communication, and solar array [K. Pister (UCB)] 6 Home Networking Driver System: 10 GOps/s 2-3 types of I/O ports (PCI, USB, Ethernet) Bus speed: 100-200MHz Bus bandwidth: 2-4 Gb/s Memory speed: 100-400MHz Core Processor: Transistors: 5-60 Million Clock frequency: 500MHz-1 GHz Area: 100-250mm2 Power: >= 50W 7 Specification of a Home Network 2005 System: (18 GOps/s) 4-5 types of I/O ports (PCI, USB, Ethernet, 802.11, IEEE 1394, Bluetooth) Area: 10-50mm2 , Power: <5W Bus speed: 400-800MHz Bus bandwidth: 10-20 Gb/s Memory speed: 400MHz-1GHz Analog part ? Core Processor: Transistors: 5-50 Million Clock frequency: 500MHz-1 GHz Area: 100-200mm2 Power: < 20W Network Processor: Transistors: 50-100Million Clock frequency: 200-800MHz (2-10 PE’s) Area: 100-300 mm2 Power: < 10W 8 Home Network in 2005 laptop Broadband modem (cable/xDSL) Ethernet Embedded gateway 802.11 HDTV IEEE1394 Bluetooth webpad Ethernet Printer pc 9 Design Challenge: What Does the Military Want A Modern Fighter/Attack Radar To Do? such as: Background*: Contribute to… by providing… Attack Mission Target acquisition Target discrimination Weapon delivery support Detect, ID, locate friend or foe AMRAAM, JDAM, etc. Survivability Situational awareness Low observability EMCON and LPI Electronic attack Navigation aid Air & surface Low RCS Power management Spoofing, jamming TF/TA Supportability High availability Small logistics footprint Long MTBF, short MTTR Min. spares kit, test set Affordability Low cost of ownership No DMS problems Low impact on the aircraft Weight, cooling * Source: Mike Lucas, Northrop Grumman such as: These broad objectives were set forth by Mike Lucas (Northrop Grumman) in his DARPA presentation last December 10 The Future Design Challenge: A Digital ESA Radar Digital ESA A/D A/D Aircraft power Power Supply Array Driver A/D Digital Beam Former A/D BSC . . . Exciter Processor/ Controller to Mission Computer * Source: Mike Lucas 11 Digital Radar Technology Directions AESA/Receiver More Channels: 1000 Higher A/D Sampling Rates: 1Gsps and Above Higher Dynamic Range: 14-15 bits Beam Forming Higher Signal Processing Throughputs: 100 of TFLOPS Continued Power Constraints: Needs 100 GFLOPS/Watt Optimized Mission Specific Processing, Low Cost ASICs High AESA to Beam Former Bandwidth: Multi Tbps Signal Processing Parallel Processing Architectures with High Bisection Bandwidth Increased Use of COTS and Standards Increased Software Reuse * Source: Mike Lucas 12 Drivers, GSRC, and C.A.D. Theme GSRC is now managed by DARPA design drivers are key Require quantified proofs of impact Also, quarterly progress reports, etc. C.A.D. Theme status + “Living Roadmap”: high perceived impact and value + Research not centrally managed, aligned freedom to do as we please + Funding this year was stable for everyone - Bookshelf fairly dormant, external participation only for $ - Metrics dormant (but, progressing in Cadence) - Integration with other Themes, FRCs is minimal Fabrics, Power/Energy, System-Level integrations should be deep/active Integrations with Interconnect, MSD, C2S2 focus centers should be deep/active Theme processes will have to change Roadmap, concrete plans, quarterly progress report roll-up Alignment with theme work Conference calls, … (other mechanisms) 13 Living Roadmap (of Application Drivers) Network, telecommunications, embedded computing systems Synchronous buses 1Gbps, differential signaling 10Gbps Network, optical interfaces have multipliers of 10x, 4x (faster than device density,speed) Train wrecks: chip-to-package and system-level interconnects (materials, signaling standards, implementation costs), power, design TAT, cost Appropriate metrics are “non-traditional”: density, cost, performance, power, and RAS (reliability, availability, and serviceability) Density: connections and bandwidth per cm(2,3) , watts/m3 Performance: How many interconnect/cm(2,3)? How long are traces? What types of signals, and what voltage levels, will meet signaling rate needs? Cost: decompositions (mother, switch/routing, control, port interface, application), and dimensions (per (gE, FC, DWDM, …) port, Gbps, MIPS, $ …) RAS: unintentionally / intentionally (for func) dropped bits/packets dropped, failure rates Many models to build and integrate: SOC integration (what is integratable, at what cost), analog circuits/DT (how badly do these fail to scale), design quality and cost, power (circuits, multi-Vdd/Vt/tox / biasing, GALS/GSLA, …), manufacturing interface (variability, NRE, layout densities, …) GTX within DT: What are the key design technology needs? Application roadmap (= ITRS System Drivers Chapter = complement to ITRS ORTCs) Application product ROI = value/cost (= attributes not yet well-defined/-measured) Impacts of Design Technology (== Metrics initiative) 14 Bookshelf Goal is to produce component-based, application-specific design methodologies and flows How will the methodology space be explored, and flows prototyped? Where are the reusable components? Open-source (understandable, reusable), malleable DT components Centered on back end, completely missing AMS capabilities, … Common data model and access mechanism (and repository?) OpenAccess source code release Design Drivers very close to vertical benchmarks (= existing Bookshelf slot) Recent overtures from IBM, LSI w.r.t. OpenAccess, working vertical benchmarks Potential work with Fabrics on snap-on flows, etc. KEY: Common DT Infrastructure Other: synergy with education in VLSI design, design technology 15 Metrics Goal: measure and improve Systems Processes Relevant system attributes / metrics System value System cost (design, production) From system ROI, have a platform from which to evaluate technology ROI Technology cost (research, advanced research, development, …) Supporting technologies / infrastructures (data mining, parameter identification, model fitting) Other: Research process What is the impact of FCRP ? (# newspaper articles? # papers? Coauthorship statistics? Survey results? Scientific health of (Design/Test, Interconnect, etc.) communities?) == part of original “Measure and Improve” goals 16 Meeting Agenda Introduction (9:00-9:30) Application driver focus of the GSRC, and implications for C.A.D. Theme C.A.D. Theme status and futures GTX (Technology Extrapolation) Tool status and current development (Mike Oliver) (9:30-9:45) Recent work (9:45-10:45) DRAM (Michael Wang (Dai)) Interconnect modeling (Xuejue Huang (King)) Global signaling (Himanshu Kaul (Sylvester)) What can GTX do to support drivers? (10:45-11:30) Bookshelf (CAD-IP Reuse) Status and summary of recent work (Igor Markov) (11:30-noon) Open Access (1:00-2:00) What can Bookshelf do to support drivers = vertical benchmarks++ ? (2:00-2:45) Roadmap for C.A.D. Theme + action items (until adjourn) 17