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ESE370:
Circuit-Level
Modeling, Design, and Optimization
for Digital Systems
Day 27: November 14, 2012
Memory Core: Part 2
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Penn ESE370 Fall2012 -- DeHon
Today
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DRAM
Leakage
Multiport SRAM
Tristate Drivers (time permitting)
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Memory Bank
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DRAM
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1T 1C DRAM
• Simplest case – Memory is capacitor
– Feature of DRAM process is ability to
make large capacitor compactly
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Penn ESE370 Fall2012 -- DeHon
1T DRAM
• What happens when read this cell?
Cbit << Cbl
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Penn ESE370 Fall2012 -- DeHon
1T DRAM
• On read, charge sharing
– VBL = (Cbit/CBL)Vstore
• Small swing on bit line
– Must be able to detect
– Means
• want large Cbit
• limit bits/bitline so VBL large enough
• Cell always depleted on read
– Must be rewritten
Penn ESE370 Fall2012 -- DeHon
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Different?
• What else is different about this?
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Dynamic Node
• Not driven
• Depend on charge staying on the node
for a period time
• Sets an upper bound on how long can
expect data to stay
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Dynamic RAM
• Takes sharing idea one step further
• Share refresh/restoration logic as well
• Only left with access transistor
and capacitor
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Penn ESE370 Fall2012 -- DeHon
3T DRAM
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3T DRAM
• How does this work?
– Write?
– Read?
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3T DRAM
• Correct operation not
sensitive to sizing
• Does not deplete cell
on read
• No charge sharing
with stored state
• All NMOS (single well)
• Prechage ReadData
• Must use Vdd+VTN on
W to write full voltage
Penn ESE370 Fall2012 -- DeHon
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Some Numbers (memory)
• Register as stand-alone element (14T)  4Kl2
• Static RAM cell (6T)  1Kl2
– SRAM Memory (single ported)
• Dynamic RAM cell (DRAM process)  100l2
• Dynamic RAM cell (SRAM process)  300l2
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Penn ESE370 Fall2012 -- DeHon
Energy
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Single Port Memory
• What fraction is involved in a
read/write?
• What are most cells doing on a cycle?
• Reads are slow
– Cycles long  lots of time to leak
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Penn ESE370 Fall2012 -- DeHon
ITRS 2009 45nm
Low Power
Isd,leak
Isd,sat
High
Performance
100nA/mm
1200 mA/mm
Cg,total
Vth
1fF/mm
285mV
0.91fF/mm
585mV
50pA/mm
560mA/mm
C0 = 0.045mm × Cg,total
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Penn ESE370 Fall2012 -- DeHon
High Power Process
• V=1V d=1000 g=0.5 Waccess=Wbuf=2
• Full swing for simplicity
• Csc = 0
– (just for simplicity, typically <Cload)
• BL: Cload=1000C0 ≈ 45 fF = 45×10-15F
• WN = 2  Ileak = 9×10-9 A
• P= (45×10-15) freq + 1000×9×10-9 W
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Penn ESE370 Fall2012 -- DeHon
Relative Power
• P= (45×10-15) freq + 1000×9×10-9 W
• P= (4.5×10-14) freq + 9×10-6 W
• Crossover freq<200MHz
• How partial swing on bit line change?
Reduce dynamic energy
Increase percentage in leakage energy
Reduce crossover frequency
Penn ESE370 Fall2012 -- DeHon
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Consequence
• Leakage energy can dominate in large
memories
• Care about low operating (or stand-by)
power
• Use process or transistors with high Vth
– Reduce leakage at expense of speed
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Penn ESE370 Fall2012 -- DeHon
Multiport RAM
Skip to admin
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Mulitport
• Perform multiple operations
simultaneously
– E.g. Processor register file
• R3R1+R2
• Requires two reads and one write
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Simple Idea
• Add access transistors to 5T
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Watch?
• What do we need to be careful about?
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Adding Write Port
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Write Port
• What options does this raise?
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Opportunity
• Asymmetric cell size
• Separate sizing constraints
– Weak drive into write port (Wrestore)
– Strong drive into read port (Wbuf)
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Isolate BL form Mem
Precharge
ReadData High
Larger, but more robust
Essential for large # of read ports
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Multiple Write Ports
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Bus Drivers
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Memory Bank
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Tristate Driver
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Tri-State Drivers
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Memory Bank
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Idea
• Memory can be compact
• Rich design space
• Demands careful sizing
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Admin
• HW5 and Proj1 graded and on blackboard
– Definitely look at what we expected on project
report
• HW6 Due tomorrow
• Project 2 out
– Milestone due Tuesday
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Penn ESE370 Fall2012 -- DeHon