Download Lecture 9: Power Analysis: Logic Level

ELEC 5270-001/6270-001(Fall 2006)
Low-Power Design of Electronic Circuits
Power Analysis: Logic Level
Vishwani D. Agrawal
James J. Danaher Professor
Department of Electrical and Computer Engineering
Auburn University, Auburn, AL 36849
http://www.eng.auburn.edu/~vagrawal
[email protected]
Fall 2006, Oct. 17
ELEC 5270-001/6270-001 Lecture 9
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Power Analysis
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Motivation:
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Specification
Optimization
Reliability
Applications
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Design analysis and optimization
Physical design
Packaging
Test
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Abstraction, Complexity, Accuracy
Abstraction level
Algorithm
Computing resources
Analysis accuracy
Least
Worst
Most
Best
Software and system
Hardware behavior
Register transfer
Logic
Circuit
Device
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Spice
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Circuit/device level analysis
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Analysis is accurate but expensive
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Circuit modeled as network of transistors, capacitors, resistors
and voltage/current sources.
Node current equations using Kirchhoff’s current law.
Average and instantaneous power computed from supply
voltage and device current.
Used to characterize parts of a larger circuit.
Original references:
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L. W. Nagel and D. O. Pederson, “SPICE – Simulation Program
With Integrated Circuit Emphasis,” Memo ERL-M382, EECS
Dept., University of California, Berkeley, Apr. 1973.
L. W. Nagel, SPICE 2, A Computer program to Simulate
Semiconductor Circuits, PhD Dissertation, University of
California, Berkeley, May 1975.
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Logic Model of MOS Circuit
pMOS FETs
VDD
a
a
Ca
c
Cc
b
Cb nMOS
FETs
Cd
Ca , Cb , Cc and Cd are
node capacitances
Fall 2006, Oct. 17
b
Da
c
Dc
Db
Da and Db are
interconnect or
propagation delays
Dc is inertial delay
of gate
ELEC 5270-001/6270-001 Lecture 9
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Spice Characterization of a 2-Input
NAND Gate
Input data pattern
Delay (ps)
Dynamic energy (pJ)
a=b=0→1
69
1.55
a = 1, b = 0 → 1
62
1.67
a = 0 → 1, b = 1
50
1.72
a=b=1→0
35
1.82
a = 1, b = 1 → 0
76
1.39
a = 1 → 0, b = 1
57
1.94
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ELEC 5270-001/6270-001 Lecture 9
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Spice Characterization (Cont.)
Input data pattern
Static power (pW)
a=b=0
5.05
a = 0, b = 1
13.1
a = 1, b = 0
5.10
a=b=1
28.5
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ELEC 5270-001/6270-001 Lecture 9
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Switch-Level Partitioning
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Circuit partitioned into channel-connected components
for Spice characterization.
Reference: R. E. Bryant, “A Switch-Level Model and
Simulator for MOS Digital Systems,” IEEE Trans.
Computers, vol. C-33, no. 2, pp. 160-177, Feb. 1984.
Internal
switching
nodes not
seen by
logic
simulator
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G2
G1
G3
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Delay and Discrete-Event Simulation
Inputs
(NAND gate)
Transient
region
a
b
c (CMOS)
Logic simulation
c (zero delay)
c (unit delay)
X
c (multiple delay)
Unknown (X)
c (minmax delay)
0
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ELEC 5270-001/6270-001 Lecture 9
rise=5, fall=5
min =2, max =5
Time units
9
Event-Driven Simulation
(Example)
a =1
c =1→0
e =1
g =1
2
2
d=0
4
b =1
f =0
Time stack
2
t=0
1
2
3
4
5
6
7
8
Scheduled
events
Activity
list
c=0
d, e
d = 1, e = 0
f, g
g=0
f=1
g
g=1
g
0
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8
Time, t
ELEC 5270-001/6270-001 Lecture 9
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Time Wheel (Circular Stack)
Current
time
pointer
max
t=0
1
Event link-list
2
3
4
5
6
7
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Gate-Level Power Analysis
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Pre-simulation analysis:
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Partition circuit into channel connected gate
components.
Determine node capacitances from layout
analysis (accurate) or from wire-load model*
(approximate).
Determine dynamic and static power from Spice
for each gate.
Determine gate delays using Spice or Elmore
delay analysis.
* Wire-load model estimates of a net by its pin-count. See Yeap, p. 39.
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Elmore Delay Model
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W. Elmore, “The Transient Response of Damped Linear Networks
with Particular Regard to Wideband Amplifiers,” J. Appl. Phys., vol.
19, no.1, pp. 55-63, Jan. 1948.
2
R2
C2
1
R1
s
4
R4
C1
C4
R3
3
Shared resistance:
R5
C3
R45 = R1 + R3
R15 = R1
R34 = R1 + R3
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C5
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Elmore Delay Formula
N
Delay at node k = 0.69 Σ Cj × Rjk
j=1
where N = number of capacitive nodes in the network
Example:
Delay at node 5 = 0.69[R1 C1 + R1 C2 + (R1+R3)C3 + (R1+R3)C4
(R1+R3+R5)C5]
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Gate-Level Power Analysis (Cont.)
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Run discrete-event (event-driven) logic
simulation with a set of input vectors.
Monitor the toggle count of each net and obtain
capacitive power dissipation:
Pcap = Σ Ck V 2 f
all nodes k
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Where:
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Ck is the total node capacitance being switched, as
determined by the simulator.
V is the supply voltage.
f is the clock frequency, i.e., the number of vectors applied
per unit
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Gate-Level Power Analysis (Cont.)
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Monitor dynamic energy events at the
input of each gate and obtain internal
switching power dissipation:
Pint = Σ
Σ E(g,e) f(g,e)
gates g
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events e
Where
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E(g,e) = energy of event e of gate g pre-computed
from Spice.
 F(g,e) = occurrence frequency of the event e at
gate g observed by logic simulation.
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Gate-Level Power Analysis (Cont.)
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Monitor the static power dissipation state of
each gate and obtain the static power
dissipation:
Pstat = Σ
gates g
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Σ P(g,s) T(g,s)/ T
states s
Where
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P(g,s) = static power dissipation of gate g for state s,
obtained from Spice.
T(g,s) = duration of state s at gate g, obtained from logic
simulation.
T = vector period.
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Gate-Level Power Analysis (Cont.)
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Sum up all three components of power:
P = Pcap + Pint + Pstat
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References:
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A. Deng, “Power Analysis for CMOS/BiCMOS Circuits,” Proc.
International Workshop Low Power Design, 1994.
J. Benkoski, A. C. Deng, C. X. Huang, S. Napper and J. Tuan,
“Simulation Algorithms, Power Estimation and Diagnostics in
PowerMill,” Proc. PATMOS, 1995.
C. X. Huang, B. Zhang, A. C. Deng and B. Swirski, “The
Design and Implementation of PowerMill,” Proc. International
Symp. Low Power Design, 1995, pp. 105-109.
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