Download Behavioral fault models

UNIT 2 : Fault Modeling
Module 2.1 Modeling Physical fault to logical fault
TOPIC : Different levels of Fault
model
Why fault model?
'''Fault models''' are necessary for
generating and evaluating a set of test
vectors.
 Generally, a good fault model should
satisfy two criteria:

1. It should accurately reflect the behavior of
defects, and
2. It should be computationally efficient in
terms of fault simulation and test pattern
generation.
Levels of abstraction in circuits

Circuits can be described at various levels of
abstraction in the design hierarchy.
◦ A behavioral description of a digital system is
given using a hardware description language, such
as VHDL or Verilog.
◦ A functional description is given at the
register-transfer level (RTL).
◦ A structural description is given at the
logic(gate) level.
◦ A switch-level description establishes the
transistor-level details of the circuit.
◦ A geometric description is given at the layout
level.
Levels of abstraction in circuits
Need of Fault models at
different abstraction levels
Fault modeling is the process of modeling defects
at higher levels of abstraction in the design
hierarchy.
 The advantage of using a fault model at the
lowest level of abstraction is that it closely
corresponds to the actual physical defects, and is
thus more accurate. However, a chip made of 50
million transistors could have more than 500
million possible defects.
 Therefore, to reduce the number of faults and,
hence, the testing burden, one can go up in the
design hierarchy, and develop fault models which
are perhaps less accurate, but more practical.

Behavioral fault models
It is defined at the highest level of
abstraction.
 They are based on the behavioral
specification of the system.
 Behavioral fault models are associated
with high-level hardware descriptions of
digital designs. They are related to failure
modes of the constructs in the hardware
description language, such as VHDL

Various behavioral fault models


The “for” clause of the language could fail.
The “switch (Id)” clause could fail in one of the
following ways:
◦ all of the specified cases are selected,
◦ none of the specified cases are selected.

An “if (Y ) then {B1} else {B2}” construct could fail in
one of the following ways:
◦ the set of statements {B1} is never executed and set {B2} is
always executed.
◦ set {B1} is always executed and set {B2} is never executed.

The “wait for S” synchronizing construct could fail such
that the clause may always be executed or never be
executed irrespective of the state of signal S.
Functional fault models
Defined at the functional block level.
 They are geared towards making sure that
the functions of the functional block are
executed correctly.
 For example, for a block consisting of
random-access memory (RAM), one type of
functional fault we may want to consider is
when one or more cells are written into,
other cells also get written into. This type of
fault is called multiple writes.

Functional fault models


Consider a multiplexer. One can derive the
following functional fault model for it.
◦ A 0 and a 1 cannot be selected on each input
line.
◦ When an input is being selected, another input
gets selected instead of or in addition to the
correct input.
Another type of functional fault model assumes
that the truth table of the functional block can
change in an arbitrary way. This usually leads to
exhaustive testing, where, for example, for an ninput combinational circuit, all the 2n vectors need
to be applied.
Structural fault models





It assume that the structure of the circuit is
known.
Faults under these fault models affect the
interconnections in this structure.
The most well known fault model under this
category is the single stuck-at fault model.
This is the most widely used fault model in
the industry.
Detection of all single stuck-at faults results
in the detection of a majority(80-85%) of
realistic physical defects
Structural fault models
The stuck-at fault (SAF) model is directly
derived from these requirements.
 A line is said to be stuck-at 0 (SA0) or
stuck-at 1 (SA1) if the line remains fixed
at a low or high voltage level, respectively
(assuming positive logic).
 If SAFs are simultaneously present on
more than one line in the circuit, the
faults are said to belong to the multiple
SAF model.

Switch-level fault models


Switch-level fault models are defined at the
transistor level.
The most prominent fault models in this
category are the stuck-open and stuck-on fault
models.
◦ If a transistor is permanently non-conducting due
to a fault, it is considered to be stuck-open.
◦ Similarly, if a transistor is permanently conducting,
it is considered to be stuck-on.

These fault models are specially suited for
the CMOS technology.
Geometric fault models

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It assume that the layout of the chip is
known.
For example, knowledge of line widths, interline and inter-component distances, and
device geometries are used to develop these
fault models.
The bridging fault model thus developed leads
to accurate detection of realistic defects.
With shrinking geometries of very large
scale integrated (VLSI) chips, this fault model
will become increasingly important.
Geometric fault models
Bridging fault models can also be defined at the
structural or switch levels. For non-CMOS technologies,
a Bridging Fault between two lines is assumed to result
in an AND or OR function being realized on the two
lines.
 These kinds of faults are referred to as wired-AND
and wired-OR, respectively

Delay fault models
Instead of affecting the logical behavior of the
circuit, a fault may affect its temporal behavior
only; such faults are called delay faults (DFs).
 Two types of DF models are usually used:

◦ The gate delay fault model: a circuit is said to have a
gate delay fault (GDF) in some gate if an input or
output of the gate has a lumped DF manifested as a
slow 0 → 1 or 1 → 0 transition.
◦ The path delay fault model: a circuit is said to have a
path delay fault (PDF) if there exists a path from a
primary input to a primary output in it which is slow
to propagate a 0 → 1 or 1 → 0 transition from its
input to its output.