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CSE 598 Nanoarchitectures Spring 2005 Lecture 1: Introduction Vijay Narayanan (www.cse.psu.edu/~vijay) Nanoarchitectures – Spring 2005 copyright Vijay Nanoarchitectures – Spring 2005 copyright Vijay What is Nanoscale? Nanoarchitectures – Spring 2005 copyright Vijay Nanoscale Dimensions Nanoarchitectures – Spring 2005 copyright Vijay Nanoscale Properties A characteristic feature of moving to the nanometer scale (besides the growing domination of quantum physical effects) is that properties of surfaces or boundary layers play an increasing role compared with the bulk properties of the material. Basic structures of nanotechnology are: Pointlike structures smaller than 100 nm in all three dimensions (e.g. nanocrystals, clusters or molecules) linear structures which are nanosized in two dimensions (e.g. nanowires, nanotubes and nanogrooves) layered structures which are nanosized in only one dimension, "inverse" nanostructures (i.e. pores) and complex structures such as supramolecular units or dendrimers. Nanoarchitectures – Spring 2005 copyright Vijay Nanoscale properties The reduction of size into the nanometer area often results in characteristic properties of substances and materials which can be exploited for new applications and which do not appear in macroscopic pieces of the same materials. significantly higher hardness and breaking strength superplasticity at high temperatures the emergence of additional electronic states high chemical selectivity of surface sites significantly increased surface energy Nanoarchitectures – Spring 2005 copyright Vijay How to achieve Nanoscale Features? There are two fundamental strategies for penetrating the nanodimension. "top-down" approach, which is predominant particularly in physics and physical technology. Here,starting from microtechnology structures and components are more and more miniaturised. "bottom-up/self-assembly" approach in which increasingly complex structures are specifically assembled from atomic or molecular components. This approach is primarily featured in chemistry and biology, where dealing with objects of the nanometer scale has long been familiar practice. Nanoarchitectures – Spring 2005 copyright Vijay Interdisciplinary by Nature Nanotechnology requires a high degree of interdisciplinary and transdisciplinary cooperation and communication. This is due to the fact that at the nano level the terminology of physics, chemistry and biology overlaps and blurs, and also to the fact that techniques from a single discipline can or must be supplemented by techniques and expertise from other disciplines. Nanoarchitectures – Spring 2005 copyright Vijay Nanoarchitectures – Spring 2005 copyright Vijay What we will cover in this class? Nanoscale CMOS technologies Process Variations, NonClassical CMOS Structures Lithography Limits, Interconnect Challenges Novel Memory Architectures SEM, FeRAM, MRAM, PRAM Nanosensor Architectures Molecular Electronics Spintronics and SET Quantum Cellular Architectures Carbon Nanotube Architectures BioChips Nanoarchitectures – Spring 2005 copyright Vijay Class Grading Midterm Exam – 30% Final Exam – 30% Class Presentations and Project – 30% Class Participation – 10% Nanoarchitectures – Spring 2005 copyright Vijay Reference Books Emerging Nanoelcetronics: Life with and after CMOS, Kluwer Academic Publishers Several Research Papers Books on Library Course Reserve in Pattee Library Nanoarchitectures – Spring 2005 copyright Vijay CSE 598 Nanoarchitectures Spring 2005 Lecture 2: Top 10 Challenges Vijay Narayanan (www.cse.psu.edu/~vijay) Nanoarchitectures – Spring 2005 copyright Vijay Silicon’s Roadmap Year 1999 2002 2005 2008 2011 2014 Feature size (nm) Chip size (mm2) Clock rate (GHz)* Power supply Vdd (V) Power (W) 180 170 1.2 1.8 90 130 214 1.6 1.5 130 100 235 2.2 1.2 160 70 269 2.8 0.9 170 50 308 3.6 0.7 174 35 354 4.4 0.6 183 For a Cost-Performance MPU (L1 on-chip SRAM cache; 32KB in 1999 doubling every two years) Specification of what must be provided if Moore’s Law is to continue to hold. * clock rates double the SIA Roadmap Nanoarchitectures – Spring 2005 http://www.itrs.net copyright Vijay Moore’s Law No. of trans./chip doubles every generation (~18 mo.) 100X increase in performance on SPECmarks in the last 10 years (from 33MHz 486 in 1990 to the 1.5GHz Pentium 4 in 2000) 20X from technology scaling 4X from architecture 1.25X from compiler technology How much longer can we track Moore’s Law ? Source: ISCA’01 Panel Nanoarchitectures – Spring 2005 copyright Vijay Gate Length Scaling Nanoarchitectures – Spring 2005 copyright Vijay Transistor Integration Capacity Transistors (Million) 1000 1 Billion 100 10 1 0.1 0.01 0.001 10 5 2 1 0.5 0.25 0.13 0.07 Technology (m) On track for 1B transistor integration capacity Is Transistor a Good Switch? I=0 I≠0 On I=∞ I=0 I = 1ma/u I≠0 Off I=0 I≠0 Sub-threshold Leakage Hot Chips Year Logic trans/Chip (M) Clock rate (GHz) Power supply Vdd (V) Power (W) 1999 15 2002 60 2005 235 2008 2011 2014 925 3,650 14,40 0 2.8 3.6 4.4 1.2 1.6 2.2 1.8 1.5 1.2 0.9 0.7 0.6 90 130 160 170 174 183 E (joules) = CL Vdd2 P01 + tsc Vdd Ipeak P01 + Vdd Ileakage Why worry about power consumption ? determines life for mobile units and . . . P (watts) = CL Vdd2 fbattery 01 + tscVdd Ipeak f01 + Vdd Ileakage Challenge #1 Sub-threshold Leakage Ioff (na/u) 10000 45nm 1000 100 10 0.25u 1 Assume: 30 50 0.25mm, Ioff = 1na/m 5X increase each generation at 30ºC 70 90 110 130 Temp (C) Sub-threshold leakage increases exponentially SD Leakage (Watts) SD Leakage Power 1000 100 2X Tr Growth 1.5X Tr Growth 10 1 0.1 0.25u 0.18u 0.13u 90nm 65nm 45nm Technology SD leakage power becomes prohibitive Leakage Power Leakage Power (% of Total) 50% Must stop at 50% 40% 30% 20% 10% 0% 1.5 0.7 0.35 0.18 Technology (m) 0.09 0.05 A. Grove, IEDM 2002 Leakage power limits Vt scaling Challenge #2 Gate Oxide is Near Limit 130nm Transistor CoSi2 Si3N4 70 nm Poly Si Gate Electrode 1.5 nm Gate Oxide Si Substrate Will high K happen? Would you count on it? Gate Leakage (Watts) Gate Leakage Power 1.E+06 1.E+05 1.E+04 1.E+03 1.E+02 1.E+01 1.E+00 1.E-01 1.E-02 1.E-03 1.5X 2X During Burn-in 1.4X Vdd 0.25u 0.18u 0.13u 90nm 65nm 45nm Technology If Tox scaling slows down, then Vdd scaling will have to slow down Energy/Logic Operation (Normalized) Energy per Logic Operation 1.E+00 1.E-01 1.E-02 1.E-03 1.E-04 1.E-05 This was Good 1.E-06 1.E-07 Slow down 1.E-08 10 5 2 1 0.5 0.25 0.13 0.07 Technology (m) Energy per logic operation scaling will slow down Challenge #4 Normalized Frequency Frequency & SD Leakage 1.4 1.3 1.2 0.18 micron ~1000 samples 1.1 30% 1.0 20X 0.9 0 5 10 15 Normalized Leakage (Isb) Low Freq Low Isb High Freq Medium Isb High Freq High Isb 20 Vt Distribution 120 0.18 micron ~1000 samples # of Chips 100 80 ~30mV 60 40 20 0 -39.71 -25.27 -10.83 3.61 18.05 32.49 VTn(mv) High Freq High Isb High Freq Medium Isb Low Freq Low Isb Vdd & Temp Variation 250 100 50 0 Heat Flux (W/cm2) Results in Vcc variation 100 90 80 70 60 50 40 Temperature Variation (°C) Hot spots Temperature (C) 150 Heat Flux (W/cm2) 200 110 Challenge #6 Exponential Costs $10,000 Litho Cost FAB Cost $10,000 $1,000 Fab Cost ($M) Litho Tool Cost ($K) $100,000 $1,000 $100 $10 www.icknowledge.com $1 1970 1980 1990 2000 2010 1960 1.E-01 1980 1990 2000 2010 $ per MIPS 1.E+03 1.E-02 1.E+02 $/MIPs 1.E-03 1.E-04 1.E+01 1.E+00 1.E-05 1.E-01 1.E-06 1.E-02 1960 1970 1.E+04 $ per Transistor $/Transistor $10 G. Moore ISSCC 03 $1 1960 $100 1970 1980 1990 2000 2010 1960 1970 1980 1990 2000 2010 Fabrication Costs Year 1999 2002 2005 2008 2011 2014 Feature size (nm) Chip size (mm2) Logic trans/Chip (M) 180 170 15 130 214 60 100 235 235 70 269 925 50 308 3,650 35 354 14,400 Cost of building factories increases by a factor of two every three years; by 2010 a fab may cost $30 billion Mask costs are growing rapidly adding more to upfront NRE for new designs next-generation lithography methods require expensive complex masks (optical proximity correction (OPC) and phase shift (PSM)) that are computationally complex to generate and that have low error tolerances multiple masks that require longer write times increase mask production costs Nanoarchitectures – Spring 2005 copyright Vijay Exploding NRE’s Mask Costs ($M) 4 3 2 1 0 250 200 150 100 Process Geometry (nm) 50 A mask set for a complex chip today can cost $500,000 (up from $100,000 a decade ago) At 150nm SEMATECH estimates that we will be entering the regime of the $1M mask set A 70nm ASIC will have $4M NRE ! Source: www.InnovationRevolution.com Nanoarchitectures – Spring 2005 copyright Vijay Optical Lithography Nanoarchitectures – Spring 2005 copyright Vijay Mask Costs Nanoarchitectures – Spring 2005 copyright Vijay Optical Proximity Correction Nanoarchitectures – Spring 2005 copyright Vijay Phase Shift Masks Selectively altering the phase of the light passing through certain areas of a photomask in order to take advantage of destructive interference improve resolution and depth of focus in optical lithography Each aperture would transmit the light passing through in such a way that it would be 180 degrees out of phase from light passing though adjacent apertures. Causes any overlapping light from two adjacent apertures to interfere destructively, thus reducing any exposure in the center ‘dark’ region. This type of phase-shifting mask, known as an alternating aperture phase shift mask. Most effective on device patterns which are highly repetitive and closely spaced, such as poly and metal layers. Nanoarchitectures – Spring 2005 copyright Vijay Challenge #7 Slow Wires Year Chip diameter (mm) Clock rate (GHz) 1999 18.4 1.2 2002 20.7 1.6 2005 21.7 2.2 2008 23.2 2.8 2011 24.8 3.6 Wire delay trends Long wires don’t scale (RC delay) - constant delay for short wires (L scales down by S > 1) Many “short wires” become “long wires” as technology scales New microarchitectures typically increase wire lengths - accessing global resources Nanoarchitectures – Spring 2005 W, H, tox L(ength) C R RC WL/tox L/WH L2/Htox 2014 26.6 4.4 Local Global Wire Wire 1/S 1/S 1/S 1/SG 1/S 1/SG S S2/SG 1 S2/SG2 S > 1 and SG < 1 for S = 1.15 and SG = 0.94, global wire delay goes up 50% copyright Vijay Scaling Module (Short) Wires R is basically constant; C falls linearly with scaling Semi-local wire resistance, scaled length Aggressive scaling Conservative scaling 0.6 0.3 pF Kohms 0.4 Semi-local wire capacitance, scaled length 0.2 Aggressive scaling Conservative scaling 0.4 0.2 0.1 0 250 180 130 100 70 50 Technology Ldrawn (nm) 35 0 250 180 130 100 70 50 35 Technology Ldrawn (nm) Source: ISCA’01 Panel Nanoarchitectures – Spring 2005 copyright Vijay Scaling Global (Long) Wires R gets quite a bit worse; C is basically constant Semi-global wire resistance, 1mm long Aggressive scaling Conservative scaling 0.6 0.3 pF Kohms 0.4 Semi-global wire capacitance, 1mm long 0.2 Aggressive scaling Conservative scaling 0.4 0.2 0.1 0 0.25 0.18 0.13 0.1 0.07 50 Technology Ldrawn (nm) 35 0 250 180 130 100 70 50 35 Technology Ldrawn (nm) Source: ISCA’01 Panel Nanoarchitectures – Spring 2005 copyright Vijay Clock Distribution Limits Clocks are long wires with big RC’s that have rigid clock skew constraints Die reachable (%) 100 1 clock 80 2 clocks 60 4 clocks 40 8 clocks 20 16 clocks 0 250 180 130 100 80 60 Processor generation (nm) Source: Matzke IEEE Computer Nanoarchitectures – Spring 2005 copyright Vijay New Interconnect Technologies Will new interconnect technologies save us? Copper interconnect allows wires to be thinner without increasing their resistance, decreasing interwire and fringe capacitance Material (-m) Silver (Ag) 1.6 x 10-8 Copper (Cu) 1.7 x 10-8 Gold (Au) 2.2 x 10-8 Aluminum (Al) 2.7 x 10-8 Material Free space Teflon AF Aromatic thermoset (SiLK) Polyimides (organic) Fluorosilicate glass (FSG) Silicon dioxide Low capacitance (low-k) dielectrics SOI (silicon on insulator) Nanoarchitectures – Spring 2005 di 1 2.1 2.6 – 2.8 3.1 – 3.4 3.2 – 4.0 3.9 – 4.5 copyright Vijay Signal Distribution Limits 10000 nm 1000 nm 100 100 nm 10 nm 10 (mm) Max Propagation Distance Even if signals could be propagated at the velocity of light, there are finite wiring distribution limits 1 0.1 0.01 0.001 0.1 1 10 it would only be possible to distribute a signal over a 15mm radius with a 1GHz clock assuming a maximum skew of 5% with a 10GHz clock that drops to 1.5mm radius 100 Driving Frequency (GHz) Nanoarchitectures – Spring 2005 copyright Vijay Challenge #8 Chip I/O Bottleneck Year 1999 2002 2005 2008 2011 2014 Logic trans/chip (M) Signal pins/chip 15 768 60 1024 235 1024 925 1280 3,650 1408 14,400 1472 Limited signal pins Logic trans/Signal pins 10000 1000 100 T=tB 10 1 1999 consume large number of pins in power/ground supplies (to combat the supply rail bounce) what happens to Rent’s Rule ? 2002 2005 2008 Year 2011 2014 p T = # signal pins/chip t average # pins/block 0 p 1 Rent exponent Normal values: 0.5 p 0.75 Source: Landman, Russo, IEEETC, 1971 Nanoarchitectures – Spring 2005 copyright Vijay Challenge #9 Reliability Year 2005 2008 2011 2014 Feature size (nm) 100 70 50 35 4 * 109 1 * 1010 Device packing 1 * 109 2 * 109 density - memory Device packing 1 * 108 2 * 108 density - logic 4 * 108 1 * 109 201? 202? 10 3 1 * 1011 1 * 1012 1 * 1010 1 * 1011 molecular scale Chip defects and transient errors will reduce the number of useful devices per unit area use redundancy to work around chip defects, but at the smallest device dimensions, transient errors due to - small number of electrons associated with each bit of information - thermal excitation of stray charge carriers, radioactive impurities, and cosmic rays may make it necessary to use redundancy on a massive scale (27-fold or even 81-fold) Thermal densities will aggravate transient errors Nanoarchitectures – Spring 2005 copyright Vijay Challenge #10 Design Costs Year 1999 2002 2005 2008 2011 2014 Feature size (nm) Chip size (mm2) Logic trans/chip (M) 180 170 15 130 214 60 100 235 235 70 269 925 50 308 3,650 35 354 14,400 Microscopic issues ultra-high speeds, clock distribution power dissipation and supply rail drop growing importance of interconnect noise, crosstalk reliability, manufacturability Nanoarchitectures – Spring 2005 Macroscopic issues time-to-market design complexity (millions of gates) IP reuse systems on a chip (SoC) design verification tool interoperability copyright Vijay 10000 1000 58%/Yr compound Complexity growth rate 100 10 Year 1997 1998 1999 2002 1 0.1 0.01 2009 2007 2005 2003 2001 1999 1997 1995 1993 1989 1987 1985 1983 21%/Yr compound Productivity growth rate Productivity (K) Trans./Staff-Mo. 100000 1981 Logic Transistors/Chip (M) 10000 1000 100 10 1 0.1 0.01 0.001 The Productivity Gap Feature Logic 3 Yr. Design Staff Size (nm) trans/chip (M) Staff Size Costs 350 6 210 $90 M 250 9.5 270 $120 M 180 15 360 $160 M 130 59.5 800 $360 M * @ $ 150K/Staff Yr. (in 1997 Dollars) Nanoarchitectures – Spring 2005 Source: SEMATECH copyright Vijay Limits to Terascale Integration “Silicon technology has an enormous remaining potential to achieve terascale integration (TSI) . . . double-gate MOSfets with gate oxide thickness of ~ 1nm, channel widths of 3nm, and channel lengths of 10nm” Meindl, Science, Sept 2001 “assuming the development and economical mass production of double-gate MOSfets. . . . The development of interconnecting wires for these transistors presents a major challenge to the achievement of nanoelectronics for TSI” Nanoarchitectures – Spring 2005 copyright Vijay Hybrid Technologies Nanotechnology may offer solutions to some of the issues with future scaling of CMOS technology. Global on-chip metal wires may be replaced with strategically located strapped on nanotubes I/O pads may be largely replaced with nanotech/MEMS sensors and actuators (chips that see, smell, hear, taste) low power nanotech alternatives for wireless communication components will emerge radically new high density, nonvolatile, on-chip storage technologies are already on the horizon. Use of nanotechnology may help to mitigate power consumption reduce mask costs (due to the use of technologies that self assemble). Nanoarchitectures – Spring 2005 copyright Vijay Nano-overview Reading The Future of Nanocomputing, Computer Aug 2003, pp 44-. Nanoarchitectures – Spring 2005 copyright Vijay CSE 598 Nanoarchitectures Spring 2005 Lecture 3: Future of Nanocomputing Vijay Narayanan (www.cse.psu.edu/~vijay) Nanoarchitectures – Spring 2005 copyright Vijay The Future of Nanocomputing – Looking Back Bandstructure Concept Effect of impurities on semiconductor properties Advances in producing high-quality crystal interfaces in silicon and germanium Devices 1948 – 1953 – 1955 – 1957 – 1959 – 1962 – bipolar transistors FET LED Tunnel Diodes ICs Semiconductor lasers Nanoarchitectures – Spring 2005 copyright Vijay Moving the ITRS Red Brick Wall New Materials Structures and channel materials such as strained silicon and silicon germanium Source-Drain materials Dopants Improved Processes High K gate dielectrics and gate materials Etching, annealing Better patterning techniques New Geometries Double gates and Trigate structures Source: G. Bourianoff Nanoarchitectures – Spring 2005 copyright Vijay Technology Limits Power dissipation limits 100 watts per sq. cm for passive cooling techniques Scaled CMOS devices manipulate electric charge as well as any research and development nanotechnologies !! Non-charge based technologies - Spin and photon fields Nanoarchitectures – Spring 2005 copyright Vijay SRC Taxanomy Source: SRC Taskforce Nanoarchitectures – Spring 2005 copyright Vijay Carbon Nanotubes Source: Computer Aug 2003 Source: Spectrum Nanoarchitectures – Spring 2005 copyright Vijay Carbon Nanotube To form carbon nanotubes, an atomic planar sheet of carbon atoms is bonded together into an array of hexagons and rolled up to form molecular tubes or cylinders with 1 to 20 nm diameters and ranging from 100 nm to several microns in length. The subthreshold slope of 70 mV per decade for the p-type transistors approaches the room-temperature theoretical limit of 60 mV. Subthreshold swing is a key parameter for transistor miniaturization since it measures how well a small swing in gate voltage can cut off current flow. Low cutoff current directly translates into low standby power—a major challenge for end-of the Roadmap devices. Nanoarchitectures – Spring 2005 copyright Vijay Silicon Nanowire quantum confinement in the transverse direction of silicon nanowires results in greater mobilities than in bulk silicon. Nanoarchitectures – Spring 2005 Keep electrons confined to a small region For more on quantum confinement http://www.ringsurf.com/info /Technology_/Nanotechnolog y/Structures.html limits the density of available phonon states and hence reduces the probability of an electron phonon-scattering event—that is, it reduces drag. copyright Vijay Why Silicon Nanowires? The performance of these isolated devices cannot in general compete with scaled silicon on speed. Their potential lies in achieving increased density and reducing fabrication costs. Proponents of cross-bar architectures argue that arrays of these devices can be “self-assembled” using fluidic assembly and Langmuir-Blodgett techniques. The major problems are in providing the gain necessary for signal restoration and fan out and to connect the self-assembled modules to global control lines. Nanoarchitectures – Spring 2005 copyright Vijay Silicon Nanowire Architectures Nanoarchitectures – Spring 2005 copyright Vijay Architectures Nanoarchitectures – Spring 2005 copyright Vijay Quantum Cellular Architecture QCA straddles the line between being a new architecture and a new device, clearly demonstrating that new architectures may be required to support new devices. In the QCA paradigm, a locally interconnected architecture consists of a regular array of cells containing several quantum dots. Electrostatic interactions, not wires, provide the coupling between the cells. When we inject an electron pair into the cell, this electron pair’s orientation defines the cell’s state. Electrical or Magnetic Nanoarchitectures – Spring 2005 copyright Vijay QCAs - Cons Grid style QCA architectures would be extraordinarily inefficient in terms of area. However, by departing from the regular grid structure, it is possible to design EQCA structures that could carry out universal computing with moderate efficiency. However, current device and circuit analyses indicate that the speed of EQCA circuits will be limited to less than about 10 MHz. Nanoarchitectures – Spring 2005 copyright Vijay Defect Tolerant Architectures The general idea behind defect-tolerant architectures is conceptually the opposite of traditional architectures Designers fabricate a generic set of wires and switches, then they configure the resources by setting switches that link them together to obtain the desired functionality. A cornerstone of defect-tolerant systems is redundancy of hardware resources—switches, memory cells, and wires—which implies very high integration density. Fabrication could potentially be very inexpensive if researchers can actualize a chemical self-assembly and attach global interconnects Nanoarchitectures – Spring 2005 copyright Vijay Fault vs defect tolerance It is important to differentiate between defecttolerant and fault-tolerant architectures. Fault-tolerant systems are designed to deal with transient faults and usually require some form of redundancy checking. Both defect-tolerant and fault-tolerant systems have an upper limit to the number of defects or faults they can handle before the correction process dominates the overall calculation efficency. The numerical limit appears to be 20 to 25 percent bad elements or defective calculations. Nanoarchitectures – Spring 2005 copyright Vijay Phase Logic Phase logic is is closely associated with the use of phase as a state variable. Richard Feynman received a patent for what he called the Parameteron in the 1950s. it is possible to store information as the relative phase of two oscillating analog signals in a tank oscillator circuit. One signal is labeled as the reference signal, and the other is labeled as the control signal. Changing the phase of the control signal relative to the reference signal “changes state” and logic. If the circuit has only two allowed relative phases, it is possible to implement both binary and multivalued logic. More recent variation is tunneling phase logic Nanoarchitectures – Spring 2005 copyright Vijay Quantum Computing The core idea of quantum information processing or quantum computing is that each individual component of an infinite superposition of wave functions is manipulated in parallel achieving a massive speedup relative to conventional computers. The challenge is to manipulate the wave functions so that they perform a useful function and then to find a way to read the result of the calculation. Implementations bulk resonance quantum implementations including NMR, linear optics, and cavity quantum electrodynamics; atomic quantum implementations including trapped ions and optical lattices; solid-state quantum implementations including semiconductors and superconductors. Nanoarchitectures – Spring 2005 copyright Vijay State Variables The search for alternative logic devices must embrace the concept of using state variables other than electric charge. molecular state spin orientation electric dipole orientation photon intensity or polarization quantum state phase state mechanical state Nanoarchitectures – Spring 2005 copyright Vijay Economic Impact Risk of adjusted return on investment of any new technology must exceed that of silicon is trivially true, Herb Kroemer, recipient of the 2000 Nobel Prize in physics, cautions, sufficiently advanced technologies will create their own applications. To estimate the total ROI for an emerging technology, in addition to markets that exist today, we also must anticipate future markets—and that’s tough. Nanoarchitectures – Spring 2005 copyright Vijay Technology Trends the bulk band structure of solids needs to be replaced by geometry-dependent energetic structures of nanostructures, requiring us toanalyze their stability and their basic quantum mechanical energy levels; doping, a bulk process, needs to be replaced by the precise manipulation and placement of individual atoms; and crystal growth, another bulk process, needs to be replaced by the self-organization of matter and selfassembly of complex structures. Nanoarchitectures – Spring 2005 copyright Vijay Next Lecture Lithography vs. Self Assembly Reading List A PROMISING LITHOGRAPHY GETS STUCK, 56-57, Spectrum January, 2004 A little light Magic, 34- , Spectrum, September 2003 Chip Makings Wet New technology, pp. 30- , Spectrum, May 2004 New Frontiers: Self-Assembly and Nanoelectronics, Computer, January 2001, pp 34- Nanoarchitectures – Spring 2005 copyright Vijay CSE 598 Nanoarchitectures Spring 2005 Lecture 4: Lithography vs. Self Assembly Vijay Narayanan (www.cse.psu.edu/~vijay) Nanoarchitectures – Spring 2005 copyright Vijay