Download Monolithic tracker - Indico

LePIX : Monolithic pixels for tracker upgrades
K. KLOUKINAS, M. CASELLE, W. SNOEYS
CERN CH-1211, Geneva 23, Switzerland
A. RIVETTI
I.N.F.N. sezione di Torino, via P. Giuria 1
Torino, 10125, Italy
A. DOROKHOV
IReS Strasbourg
P. CHALMET, H. MUGNIER, J. ROUSSET
MIND-MicroTechnologies-Bât. Le Mont Blanc
74160, Archamps, France
Walter Snoeys – CERN – PH – ESE – ME-2009
1
A monolithic detector in standard very deep submicron CMOS technology



‘Traditional’ monolithic detectors:
 non-standard processing on very high resistivity substrate
Les tests de production
or
 MAPS based with serial readout not necessarily compatible with future colliders, and
with collection by diffusion very much affected by radiation damage
Feedback from foundry that substrate sufficiently lowly doped is available in very deep
submicron technologies (130 nm and beyond), 10 micron depletion no problem, strong
perspectives to obtain significantly more
First time there is an opportunity to integrate detector with very advanced standard CMOS
Readout
circuit
Collection
electrode
Sensitive layer
High
energy
particle
Walter Snoeys – CERN – PH – ESE – ME-2009
2
Goal of LePIX
Exploiting the features of very deep submicron CMOS processes to combine most of
the advantages of the previous technologies:
 Good radiation hardness (charge collection by drift).
 High speed: parallel signal processing for every pixel, time tagging at the 25ns level.
 Low power consumption: target 20 mW/cm2 in continuous operation.
 Monolithic integration.
 Use of CMOS technologies with high production rate (20 m2 per day…) and cost per
unit area less than traditional detectors
 Significant advantages beyond 130 nm (low K dielectrics in the metal stack)
 Lepix is a collaboration between CERN, IReS in Strasbourg, INFN, C4i-MIND in
Archamps and interest from Imperial College.


Within INFN it is a project funded by the R&D scientific committee
C4i-MIND is financed by the Dept. de la Haute Savoie.
Walter Snoeys – CERN – PH – ESE – ME-2009
3
Device design: uniform depletion layer
Collection
electrode
High
energy
particle
Collection
electrode
High
energy
particle
 Challenge is in obtaining a uniform depletion layer.
 Optimal geometry and segmentation of the read-out electrode.
 Effective charge resetting scheme.
 Pattern density rules in very deep submicron technologies are very restrictive.
 Insulation of the low-voltage transistors from the high voltage substrate.
Sensor is designed in close contact with the foundry!
Collection by drift will limit charge sharing and reduce cluster size
Walter Snoeys – CERN – PH – ESE – ME-2009
4
Device design: uniform depletion layer
Pixel pitch used in this 2D simulation was 50 mm.
With the highest resistivity substrate available 80 mm depletion with 100 V
Walter Snoeys – CERN – PH – ESE – ME-2009
5
Analog power
1
Noise ~
gm
1
~
Im
Signal-to-Noise ~
where m < 1/2
Weak dependence of the noise on current !
For constant signal to noise
Current I per channel :
Segmentation
Number of elements N, C~1/N:
I
-m
~
Q
C
Q x Im
C
2…4
or I ~ (C/Q)
Weak … Strong inversion
1…3
2…4
Total analog Power ~ N(C/Q)
~ (1/N)
Higher segmentation is (very) good
Decreased depletion layer thickness -> need to segment in proportion
Xd ÷ 2 -> C ÷ 2
Note: will saturate for very high segmentation
Walter Snoeys – CERN – PH – ESE – ME-2009
6
Analog power
 10 mW/cm2 = 1 microW/(100x100 micron)
 Example: Basic element of 100x100 micron with 1 mA of
current (so we split elements to optimize power to signal/noise
ratio)
n+
- +
- +
- +
- +
- +
- +
- +
- +
- +
- +
- +
p=
- +
 Take transistor noise at 40 MHz BW
Veq  0.16mV
S
Q
4 fC 0.4 fC 0.04 fC
 25   4mV 


N
C
1 pF 0.1 pF
10 fF
Collection depth
300 mm
30 mm
3 mm
Could fit both monolithic and non-monolithic approach !
V=
Walter Snoeys – CERN – PH – ESE – ME-2009
7
Device simulations
 Need to work on Q/C: 10 micron depletion layer established, means:
0.13 fC
S
Q
 25   4mV 
N
C
33 fF
 33 fF achievable (cfr CMOS imagers order of magnitude less, but smaller…)
 We are working with IN2P3 Strasbourg on device simulations for the detecting element:
 Worked on convergence of simulations at high reverse bias
 Now using 2D simulations to verify principles (less computation intensive)
 First results (2D, verif in 3D to be done) indicate high biases 100 V should be
possible, so ~ 30 micron depletion or even more
 Working to obtain uniform depletion layer even with small collection electrode
Walter Snoeys – CERN – PH – ESE – ME-2009
8
Front end for monolithic in 90nm
 ‘Minimal’ cell which sends current signal out: Use
metal lines as capacitors in a current mode front
end. Can have 10 000 elements per square cm
(100 x 100 mm2 per element)
 Need fine metal pitch to create all the busses (one
line per element !)
Iout
Comp in
 Advantage: minimal activity/power consumption
within matrix, but large data processor at the edge
of the chip
 Simulations started:~ 900 nA for integrated amplifier
– shaper + comparator
 Few modeling questions related to very deep
submicron technology. Studied parasitic extraction
to verify against measurements.
 Note: compared to present day pixel detectors
important savings in power, but less S/N (maybe
some of this can be recovered, depends on Q/C
finally achieved)
Walter Snoeys – CERN – PH – ESE – ME-2009
Comp out
After inverter
9
More accurate time tagging using Time over Threshold
Time over threshold
 ENC 40 electrons rms.
 SNR of 15 for 600 electron
signal.
Time walk
 Response delay of 50 ns
for 600 electrons.
Minimum signal to have response within 25 ns is about 2500 electrons.
Time over threshold can be explored to recover the timing. Trade-off between
digital and analogue power consumption. Can also be used for analog signal and
position resolution
Walter Snoeys – CERN – PH – ESE – ME-2009
10
Save analog power, how about digital ?
Challenge is efficient data processing at the
edge of the chip and communication to the
outside for trigger and tracking signals
Matrix
Occupancy
CMS
D. Abbaneo
Line up and down for every cell
Data processor
Chip
PXB Layer 1
PXB Layer 2
PXB Layer 3
TIB Layer 1 int
TIB Layer 1 ext
TIB Layer 2 int
TIB Layer 2 ext
TIB Layer 3 int
TIB Layer 3 ext
TIB Layer 4 int
TIB Layer 4 ext
TOB Layer 1
TOB Layer 2
TOB Layer 3
TOB Layer 4
TOB Layer 5
TOB Layer 6
Element
100x100
micron
5.56E-03
2.41E-03
1.39E-03
3.39E-04
2.82E-04
2.18E-04
1.88E-04
1.28E-04
1.14E-04
9.32E-05
8.55E-05
5.94E-05
4.58E-05
3.54E-05
2.78E-05
2.57E-05
1.97E-05
Superelement
256x100x100
micron
1.42E+00
6.16E-01
3.55E-01
8.69E-02
7.23E-02
5.58E-02
4.82E-02
3.29E-02
2.91E-02
2.39E-02
2.19E-02
1.52E-02
1.17E-02
9.06E-03
7.11E-03
6.58E-03
5.05E-03
In the following some ideas on architecture –
not final at all, would like to point out the
thinking, do not want to give impression things ALICE: inner layer 200 tracks/sq cm,
are fully solved…
or 0.02 for 100x100 micron…
Walter Snoeys – CERN – PH – ESE – ME-2009
11
Data processor
Trigger data generation
Trigger data
(40 MHz)
Storage until level 1
Tracking data generation
Tracking data
(<100 kHz)
 Advantages of having all bits at the edge:
 Can handle them in a programmable way
 Trigger: from ‘fast or’, could also have fast multiplicity, topological …
 Do not need to distribute the clock to all elements (cannot would take a
good fraction of 10 mW/sq cm), save power by not doing so
Walter Snoeys – CERN – PH – ESE – ME-2009
12
Prototyping

Foundry proposed alternative using MPW instead of engineering run for prototyping. Means
significant cost savings. We are in contact with the MPW service and are finalizing the details.

Would like to pursue this route, and submit a prototype as soon as possible. First possible
submission date is October (run got cancelled, will submit in February).

List of items for the submission:

Test structures to characterize the substrate doping, structures allowing resistance
measurements, some diodes, etc…

Transistor test structures for model verification, and for irradiation measurements.
(First version almost finished, previously submitted to other foundry as well)

ESD test structures

A matrix in a few variants with MAPS readout compatible with existing test setups

A matrix in a few variants with a fast shaping front end. Both types of matrices will be
equipped with test cells which can receive an electrical test input, and of which some
are connected to buffer amplifiers capable of driving the signals off-chip.

Pixel pitch now 50 microns
Walter Snoeys – CERN – PH – ESE – ME-2009
13
Conclusions
 Perspective for monolithic in standard deep submicron with several advantages
 Could consider thinning, detector and readout chip combined, stitching possible but needs
further evaluation including yield considerations
 Analog power can be reduced by segmentation, need work on digital, would like to exploit
having all pixel signals at the bottom of the matrix, in general power will be key to reduce the
material, would like to stay below 20mW/sq cm for continuous readout.
 Would like to exploit signal from every pixel at the periphery. Default now is binary readout
with 25 ns resolution, but we are studying also analog information (position resolution and
better time tagging). For the moment pixel pitch is 50 microns.
 Charge collection by drift
 Possibility for prototyping with MPW in 90nm even on more lightly doped substrates
 Working on the first submission, some delay (submission now in February)
 CERN committed to at least ¼ of the material cost, INFN approved funding, funding of
engineering time from the Conseil General de la Haute Savoie, contribution from IN2P3
 Interest from ALICE and CMS, some discussions with ATLAS, CLIC ?
 Very much work in progress, in the early phases of development
Walter Snoeys – CERN – PH – ESE – ME-2009
14