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VERY HIGH
PERFORMANCE
LOGIC
Digital Integrated Circuits
High Speed
© Prentice Hall 1995
Note
Slides on High-Speed Bipolar
and Superconduction not yet
available
Digital Integrated Circuits
High Speed
© Prentice Hall 1995
GaAs Design
Increased Mobility at Low Electrical Field
Higher Performance
Digital Integrated Circuits
High Speed
© Prentice Hall 1995
GaAs Material Properties
• Max electron velocity = 2 x Silicon = 2  107 cm/sec
• Hole mobility GaAs (= 400) < Si (489 cm2 V/sec)
Excludes complementary logic
• Electron mobility GaAs (4000-9000) >> Si (500-1200)
• Maximum Field (max velocity) GaAs (0.3 V/m) < Si (1 V/m)
Should operate at low voltages
• Shottky Barrier Height GaAs (0.6-0.8V) > Si (0.4-0.6 V)
• Bandgap Energy GaAs (1.43 eV) > Si (1.11 eV)
Radiation hard
• Resistivity GaAs (1.109 /sq) >> Si (1.105 /sq)
Semi-insulating
Digital Integrated Circuits
High Speed
© Prentice Hall 1995
GaAs Material Problems
• Brittle Material  3 to 4 inch wafers
• High Defect Density
Low Yield (100 to 1000 times smaller vs. Si)
• QSS and Qox large
NO MOS transistors!
• Hole mobility low
No complementary gates
Digital Integrated Circuits
High Speed
© Prentice Hall 1995
Favored Device: MESFET
G
S
depletion region
Schottky Diode
n+
D
T
n
L
Semi-Insulating GaAs
Digital Integrated Circuits
High Speed
n+
channel
1017cm-3
 = 1000-2000 /sq
© Prentice Hall 1995
MESFET Operation
if(VG == 0): transistor ON — part of channel depleted
if (VG): depletion layer   conductivity 
if (VG ): depletion layer   conductivity 
if (VG == VP): pinchoff, no conductance
DEPLETION TRANSISTOR
Enhancement transistors also available
VP (enhancement): 0 V— 0.2 V
VP (depletion): -0.7 V — -2 V
Large variations of VP over die (100 — 200 mV)!
Digital Integrated Circuits
High Speed
© Prentice Hall 1995
I-V Characteristic
VGS =0.7V
0.35
0.5
ID
ID (mA)
ID (mA)
0.6V
0.3
0.5V
0.15
0.4V
IG
0.1
0.3V
-0.05
0
0.5
1.0
VDS (V)
1.5
2.0
-0.1
0
0.4
VGS (V)
0.6
0.8
(b) ID-VGS characteristic (VDS = 0.5 V)
IG is the current flowing into the gate.
(a) I D-VDS characteristic
Digital Integrated Circuits
0.2
High Speed
© Prentice Hall 1995
Curtice Model
Digital Integrated Circuits
High Speed
© Prentice Hall 1995
GaAs MESFET Model
.model enh njf
+ vto=0.23 beta=250u lambda=0.2 alpha=6.5 ucrit=0 gamds=0
ldel=-0.4u wdel=-0.15u
+ rsh=210 n=1.16 is=0.5m level=3 sat=0 acm=1 capop=1
.model dp njf
+ vto=-0.825 beta=190u lambda=0.065 alpha=3.5 ucrit=0 gamds=0
ldel=-0.4u wdel=-0.15u
+ rsh=210 n=1.18 is=10m level=3 sat=0 acm=1 capop=1
Digital Integrated Circuits
High Speed
© Prentice Hall 1995
Buffered FET Logic (BFL)
Input Stage
Level Shifting Output Stage
VDD
VDD
0.6Ws
kWs
Inv
In1
In2
Ws
Out
kWs
VSS
Digital Integrated Circuits
High Speed
© Prentice Hall 1995
Voltage Transfer Characteristic
4.0
Vinv
V
2.0
0.0
Vout
-2.0-2.0
Digital Integrated Circuits
-1.0
Vin (V)
High Speed
0.0
1.0
© Prentice Hall 1995
Direct-Coupled Fet Logic (DCFL)
VDD
Out
In1
In2
Max Input Voltage : +/- 0.7 V
Strict Control of Threshold Voltage Required (+/- 0.1 V)
Asymmetrical Response
Sensitive to Fanout
Digital Integrated Circuits
High Speed
© Prentice Hall 1995
Performance versus Power
Digital Integrated Circuits
High Speed
© Prentice Hall 1995
Source-Coupled FET Logic (SCFL)
Output Stage
RD
RD
In2 -
In 2+
Out +
Out -
In1-
In 1+
ISF
I SS
IS F
VSS
Digital Integrated Circuits
High Speed
© Prentice Hall 1995
Logic Families - Comparison
Digital Integrated Circuits
High Speed
© Prentice Hall 1995
High Electron Mobility Transistor
High Electron Mobility
Transistor (HEMT)
(HEMT)
SOURCE
DRAIN
GATE
Undoped AlGaAs
n+ GaAs
0-500 Å
n+AlGaAs
350-500 Å
20-80 Å
Undoped semi-insulating GaAs
Two-dimensional
electron gas
Mobility in Undoped GaAs > 8500 cm 2/Vsec (4500 cm2Vsec in Doped GaAs)
Up to 50,000 cm2/Vsec at Liquid Nitrogen Temperature
Digital Integrated Circuits
High Speed
© Prentice Hall 1995
JJ Logic Families
IBIAS
VA RL
VB
RL
IBIAS
RL
IBIAS
RL
(a) Current injection gate
IBIAS
IBIAS
IBIAS
IBIAS
reset phase
IA
IB
(c) bias current waveform
RL
(b) Magnetically coupled gate
Digital Integrated Circuits
High Speed
© Prentice Hall 1995
MVTL Gate Layout
RD
M
Out
J1
Rin1
In1
Rin2
In2
Vbias
J2
J3
Rbias
Digital Integrated Circuits
High Speed
Ri
© Prentice Hall 1995
MVTL Transient Response
Volt x 10-3
2.00
Digital Integrated Circuits
V bias
1.80
1.60
1.40
1.20
1.00
0.80
0.60
0.40
0.20
-0.00
-0.20
-0.40
Vin1
Vout
0.00
200.00
High Speed
Seconds x 10
-12
© Prentice Hall 1995