Download Pixel-level delta-sigma ADC for VISA

Pixel-level delta-sigma ADC with
optimized area and power for
vertically-integrated image sensors
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Alireza Mahmoodi and Dileepan Joseph
University of Alberta, Canada
Email: [email protected], [email protected]
Outline
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 Motivation
 Pixel-level ADC
 Vertically-integrated sensor arrays (VISA)
 ADC choice
 Delta-sigma ADC
 Modulator
design
 Decimator design
 Simulation results
 Conclusion
Motivation (improve SNR in log sensors)
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Log
sensors
Linear
sensors
DR
SNR
low SNR but high DR
good SNR but low DR
 How to improve SNR in log sensors?
Ans: pixel-level delta-sigma ADC.
Images © IMS Chips
http://www.ims-chips.de/
Pixel-level ADC (lowers temporal noise)
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Advantages:
 Lower read noise means higher SNR is achievable;
 Digital pixel output means analog performance, hence
image quality, not limited by settling of column bus.
Drawbacks:
 More transistors means lower spatial resolution;
 More transistors means fixed-pattern noise (FPN) due
to mismatch variation could be much worse.
Vertically-integrated sensor arrays
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Main issue with pixel-level ADC is a large pixel size.
 With vertical integration, photodetectors are above
processing circuits—they do not compete for area.
 VISA makes leading-edge CMOS “usable” for imaging.
 Pixel-level ADC in VISA may be the best way to achieve
high SNR, high DR, high frame rate, and small pixels.

Conventional pixel
Pixel in VISA
ADC choice
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 Nyquist rate ADCs:
Flash, successive approximation, etc;
 Must filter temporal noise before sampling.
 Delta-sigma ADCs:
 Filters temporal noise after oversampling;
 Relies mainly on digital signal processing—

 Suitable
for leading-edge CMOS and
 Robust to mismatch variation;
Can eliminate quantization nonlinearity;
 Frame rate and bit resolution may be traded.

Nyquist rate and delta-sigma ADCs
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First-order delta-sigma ADC
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 First order delta-sigma is simple with minimum area
and, surprisingly, minimum power consumption.
 Unlike higher order structures, first order delta-sigma is
not sensitive to capacitor mismatch. Therefore, small
capacitors may be used, which saves power
Analog input
+
+
-
∫
Digital output
Quantizer
Decimator
Previous works
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 Pixel-level delta-sigma was implemented by Fowler et al.
Decimation was done at chip level, which meant a very
high and impractical output bit rate from pixels.
 A similar work was demonstrated by McIlrath but it
cannot support high SNR. Frame rate would also be
limited for high DR (dynamic range) operation.
 Previous works could apply to linear sensors but not to
logarithmic sensors. This work applies to both.
 In this work, we design a delta-sigma ADC to fit inside a
pixel of 32 μm × 31 μm, decimator included.
Modulator design
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 We started (prev. paper)
with column-level ADC,
where area is irrelevant.
 The same method was
used to design the circuit
for pixel-level ADC.
 Modulator was designed to
achieve an SNR of 80 dB at
a frame rate of 50 Hz.
 Very small capacitors were
used (20 fF and 60 fF).
Operational trans-conductance amplifier
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 We designed a folded-cascode OTA with common-mode
feedback (CMFB), according to our previous work.
 Compared to column-level ADC, lower speed of pixellevel ADC meant gain boosting was not required.
Decimator design
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 Decimator is needed to low-pass filter the modulator
output and down sample it to the Nyquist rate.
 Different methods for decimation are possible but we
chose a one-stage FIR filter to minimize area.
 Coefficients of optimal filter are generated at chip level,
and are broadcast in bit-serial fashion to all pixels.
 In each pixel, one-bit modulator output is convolved with
multi-bit filter coefficients using a serial accumulator.
In-pixel decimation
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 AND gate suffices to
implement multiplier
for convolution.
 When modulator
output is one,
coefficients are
accumulated.
 Accumulation is done
serially so a 1-bit adder
can do 19-bit addition.
Register design
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 A 19-bit register is needed, which means 19 D flip-flops.





They comprise the bulk of the decimator circuit.
A D flip-flop designed at gate level needs 34 transistors.
A standard D flip-flop, with reset capability, designed at
transistor level in CMOS needs 22 transistors.
Using two pulsed latches with two non-overlapping
clocks, a design is possible with only 8 transistors.
Fewer transistors may be used at the cost of more clocks
but the savings would entail diminishing returns.
The size of the register may also be reduced by reducing
the target SNR, which was 80 dB in this case.
Schematic of D flip-flop
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 When the output is high, a subthreshold current could
charge node A, which would change the output to low.
 In the worst case, a bit error would occur after 150 μs.
 But each node is refreshed every 1 μs, as the clock
frequency is 1 Mhz. So the chance of error is low.
vdd
vdd
vdd
vdd
input
A
output
clk1
clk2
gnd
gnd
Simulation results (1)
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 The design was laid out and fabricated in a standard




0.18 μm CMOS process with six metal layers.
The proposed ADC has an area of 32 μm × 31 μm, on the
order of VISA pixels for infrared cameras.
Simulation results for DC input signals, within the 0.6 V
input range, shows the SNR is limited to 80 dB.
The power consumption is 680 nW per pixel. For a one
megapixel sensor and a frame rate of 50 Hz, the power
consumption would be 680 mW for all pixels.
We received the fabricated ADC a few weeks ago and it
appears to be working. The measured performance will
be reported in due course (not in these slides).
Simulation results (2)
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Quantization noise (μV) versus
input signal level (V):
• Theory calculation (22 μV);
• Behavioral simulation (9 μV);
• Circuit simulation (16 μV).
Power consumption (nW) versus
input signal level (V):
• Modulator (120 nW);
• Decimator (560 nW).
Layout and fabrication
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Pixel-level ADC,
modulator and decimator:
32 μm × 31 μm
The entire chip: 1 mm × 2 mm
Conclusion
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 A first-order delta-sigma ADC of size 32 μm × 31 μm




for pixel-level data conversion was designed.
Simulation shows it has a power consumption of 680
nW and an SNR of 80 dB at a frame rate of 50 Hz.
The decimation is done serially inside the pixel to
reduce the output bit rate with minimum area.
Experimental results are still to come but the ADC has
been fabricated and appears to be working.
Eventually, the ADC will be used in a logarithmic
sensor to achieve high SNR and high DR.
Acknowledgements
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 The authors gratefully acknowledge the support of the
Natural Sciences and Engineering Research Council of
Canada, as well as CMC Microsystems.