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Simplified Transistor - Transistor Logic (TTL)
*
*
*
iR
+
vo
*
vi
ECES 352 Winter 2007
Transistor - Transistor Logic (TTL)
Simplified form of inverter
 Two instead of four transistors
 Two instead of four resistors
For low vi input, output vo is high
 Q1 is on (saturation).
 Q3 is off (cutoff).
 So vo = VCC - iC RC ≈ VCC
For high vi input, output vo is low
 Q1 is off (inverse mode).
 Q3 is on (saturation).
 So vo = VCC - iC3 RC is small.
 Q3 driven into saturation region
so vo = VCE,sat ≈ 0.2V.
Ch 11 Bipolar Digital Pt. 2
1
Simplified Transistor - Transistor Logic (TTL)
*
vo
vi
ECES 352 Winter 2007
Assumptions for analysis:
 All transistors are npn and identical.
 For p-n junctions in transistors to be
conducting current,
 VBE or VBC must be 0.7V or higher.
 For smaller junction voltages,
current flow is negligibly small.
 For transistors in forward active mode,
 iC = β iB,
 VBE,active ≈ 0.7 V
 For transistors in forward saturation
mode,
 VBE,sat ≈ 0.8 V.
 VCE,sat ≈ 0.2 V.
 iC < β iB or iC / iB < β.
 For transistors in inverse mode
(E junction reverse biased, C junction
forward biased),
 current gain is very small
 iE = βr iB
 βr is very small, e.g. βr ~ 0.02
Ch 11 Bipolar Digital Pt. 2
2
Simplified Transistor - Transistor Logic (TTL)
Low Input, High Output
Load inverter
VCC = 5V
Driving
inverter
+
VB1 =
0.7V+0.2V
= 0.9V
VCC = 5V
*
iR
.
R=4K
VBE1= + p
+ VBC1
0.7V
n
n
iE1
*
*
+
v*o
n
p
+
iC1 VBE3
n
vo=VCE,sat
= 0.2 V
*
I
Q3 in
saturation
V
ECES 352 Winter 2007
0.7 V
For low vi input, output vo is high
Q3 of driving inverter is in saturation
so vo = VCE,sat = 0.2 V = vi of Q1
Transistor Q1 (Load Inverter)

E jcn forward biased (VBE1 = 0.7 V ).

C jcn only weakly forward biased (VBC1 = ? ).

Q1 in saturation (VCE1= VCB1 + VBE1 = -VBC1 + VBE1
≈ -0.45V + 0.7V = 0.25V) and iC1 < β iB1.
Transistor Q3 (Load Inverter)

How do we find VBC1?

VB1 = VBC1 + VBE3 = 0.9 V

Assuming VBC1 ≈ VBE3 , then both = 0.45 V

So E jcn of Q3 forward biased, but not enough
so iB3 ≈ 0 and Q3 is off (iC3 ≈ 0).

RC iC3 ≈ 0 and vo ≈ VCC = 5 V.
Current iR flows through R and out the input

Size of iR?
iR = (VCC - VB1 )/R
= (5 V - 0.9 V)/4K=1 mA

Where does it go?

Virtually all of the current flows out emitter of
Q1 , iR ≈ iE1 = 1mA

This current flows into the collector of Q3. of the
drive inverter (out the input).
Ch 11 Bipolar Digital Pt. 2
3
Simplified Transistor - Transistor Logic (TTL)
High Input, Low Output
VCC = 5V
VCC = 5V
*
*
Driving
inverter
iR
VB1 =
5 V-iRR
.
RC =
1.6K
R=4K Ic3 =
3 mA
p+V
VBE1< 0 +
BC1
n
Q3 in
cutoff
+
iE1 ≈ 0
n
p
+*
vo
+
n
iC1 ≈ iB3 VBE3
n
vo=VCC
=5V
iC
I
Saturation
iC/iB < 
active
V
0.7 V
ECES 352 Winter 2007
vCE
Q3 in driving inverter is in cutoff so vo = VCC = 5 V =
vi of Q1
Transistor Q1 (Load Inverter)

E jcn rev. biased (VBE1 = 0.7V, VBE1 < 0).

C jcn forward biased (VBC1 = ? ).

Q1 in inverse active mode and iE1 = βr iB1 ≈ 0,
since βr is very small, e.g. βr ~ 0.02
Transistor Q3 (Load Inverter)

How do we find VBC1?

Know VB1 = VBC1 + VBE3

Assuming iR flows through C junction of Q1
and into the base of Q3, then
VBC1 ≈ VBE3 ≈ 0.7 V so
iR = (VCC - VBC1 -VBE3)/R
= (5 V- 1.4 V)/4K = 0.9 mA

So E jcn of load’s Q3 is forward biased,
iB3 ≈ iR = 0.9 mA = 900 µA!

If Q3 in active mode, iC3 = β iB3 and for β = 50,
then iC3 = 50(0.9 mA) = 45 mA.

Is this possible? NO! Why?
vo= VCC - iC3 RC = 5 V - 45 mA (1.6K)
= 5V - 72V = - 67V < 0 ! Not possible !

So Q3 must be in saturation mode since the
base current is very large (900 µA), where
vo= VCE,sat ≈ 0.2 V; so
iC3 =(5V-0.2V)/1.6K= 3mA. This verifies that Q3
is in saturation since iC3 = 3 mA < β iB3 = 45 mA.
Ch 11 Bipolar Digital Pt. 2
4
Simplified TTL Transfer Characteristic
VCC = 5V
VB1 =
0.7V+vi
+
vi
iR
.
*
*
VCC = 5V
RC =
1.6K
R=4K
iC3
VBE1= + p
+ VBC1
0.7V
n
p
+
n
iE1
iC1 = iB3 VBE3
n
+
vo
*
n
vo
A B
*
VCC = 5V
I
Region I (A to B) (Low vi, high vo )
Q1 is in forward saturation
 E jcn forward biased (VBE1 = 0.7 V and base
current is large, iB1 = iR1 = 1 mA ).
 C jcn is weakly forward biased (VBC1 = 0.45 V ),
so Q1 in saturation mode.
 VCE1= VCB1+VBE1 = -VBC1+VBE1 ≈ -0.45 + 0.7 ≈ 0.25V
 Current iR is flowing out the input.
Q3 is biased in forward active mode, but
only weakly (not on since VBE3 < 0.7 V).
 VB1 = vi + 0.7 V
 Assuming VBC1 ≈ VBE3 , then both are equal to
(0.35 V + vi /2) ~ 0.45V < 0.7 V.
 So E jcn of Q3 is forward biased, but not
enough so iB3 ≈ 0 and Q3 is off.
 Then iC3 ≈ 0 and vo ≈ VCC = 5 V.
Note
 iR = (VCC – VCE3,sat –VBE1)/R
= (5 V - 0.2V - 0.7V)/4K = 1.0 mA
 Since iC1 = iB3 ≈ 0, nearly all of this current is
going out the E of Q1 so iE1 ≈ iR = 1.0 mA.
vi
ECES 352 Winter 2007
Ch 11 Bipolar Digital Pt. 2
5
Simplified TTL Transfer Characteristic
VCC = 5V
iR
VB1 =
0.7V+vi
+
vi
.
RC =
1.6K
R=4K
iC3
VBE1= + p
+ VBC1
0.7V
n
p
+
n
iE1
-iC1 = iB3VBE3
vo
n
vo
n
*
A B
VCC = 5V
I
VCE3,sat
= 0.2V
*
*
*
VCC = 5V
Region II (B to C) (Transition region)
Q1 is still in saturation.
Q3 initially is biased in forward active mode, but
weakly (VBE3 < 0.7 V).
 When does this change?
 When vi = 0.6 V, then VB1 = vi + 0.7 V = 1.3 V
+ so VBC1 ≈ VBE3 = 0.65 V and these p-n
junctions can begin to conduct current.
 This current comes thru R as iR.
 This provides the base current for Q3 to
begin to turn on and so the collector
current iC3 rises and the output voltage
starts dropping according to
vo= VCC - iC3 RC = 5 V - iC3 (1.6K)
Note the size of iR is about the same as before,
i.e. iR = (VCC - VBC1 -VBE3)/R = (5 V- 1.3 V)/4K = 0.93
mA. Most of this current is still going out the
gate input (E of Q1 ) since iB3 starts out very
small (~μA’s).
II
C
0.6 V 0.7V
ECES 352 Winter 2007
vi
Ch 11 Bipolar Digital Pt. 2
6
Simplified TTL Transfer Characteristic
*Where is point C?
VCC = 5V
iR
VB1 =
0.7V+vi
+
vi
.
*
*
*
VCC = 5V
RC =
1.6K
R=4K
iC3
VBE1= + p
+ VBC1
0.7V
n
p
+
n
-i
=
i
V
C1
B3 BE3
i
E1
n
+
vo
*
n
*
vo
iC
A B
VCC = 5V
C
I
VCE3,sat
= 0.2V
Q3
II
*
active
Region II (B to C) (Transition region)
Q1 initially in saturation
Q3 initially is biased in forward active mode, but only
weakly on since VBE3 < 0.7 V.

For Q3, as vi rises, the base current iB3 rises, iC3
rises and the output voltage drops.
vo= VCC - iC3 RC = 5 V - iC3 (1.6K)
Where is point C?

When vi = 0.7 V, then VB1 = VBC1 + VBE3 = vi + 0.7 V
= 1.4 V so VBC1 ≈ VBE3 = 0.7 V and these p-n jncs
can conduct large currents.

As vi rises from 0.6 V to 0.7 V, more and more
of iR (0.9 mA) goes into the base of Q3 and it
enters further into the active mode.
At C, Q3 reaches the edge of saturation, vo = VCE,sat =
0.2 V, so iC3 = (5V - 0.2)/1.6K = 3 mA. Then iB3 = iC3 /β =
3mA/50 = 60 μA. So only 60 μA of iR (~ 1 mA = 1000 μA)
needs to be diverted into the base of Q3 to drive it
into saturation!
So at point C most of iR is still going out the gate’s
input (E of Q1), since iR = 0.9 mA and iB3 = 60 μA.
Saturation
iC/iB < β
iB 3 60A
60A


 0.067  6.7%
iR 0.9mA 900A
C
0.6 V 0.7V
ECES 352 Winter 2007
vi
A,B
vCE
Ch 11 Bipolar Digital Pt. 2
7
Simplified TTL Transfer Characteristic
VCC = 5V
iR
VB1 ≈
1.4V
.
VBE1
+
vi
n
iE1
RC =
1.6K
R=4K
+ p+
*
*
VCC = 5V
iC3
+
vo
n
VBC1
n
p
+
iC1 = iB3 VBE3
n
*
vo
iC
VCC = 5V
0.2V
0.1V
A B
I
D
II III
C
0.6 V 0.7V
ECES 352 Winter 2007
Saturation
iC/iB < β
D
5V
vi
C
Q3
active
Region III (C to D) (Low output region)
Q1 initially still in saturation at C
 As vi rises above 0.7V, VB1 is nearly
constant at 1.4V, so E junction of Q1
becomes less forward biased and then
eventually becomes reverse biased.
 C junction is forward biased, so Q1
moves from forward active to inverse
active mode where iE1 = βr iB1
where βr = 0.02 << β = 50.
Q3 is entering saturation at C, VBE3 ≈ 0.7 V
 For Q3, as vi rises above 0.7 V, VB1
rises slowly to 1.6 V as vi rises to 5 V.
 When VB1 ≈ 1.6 V,
then VBC1 ≈ VBE3 = 0.8 V = VBE.sat.
 At VBE3 = 0.8 V, iB3 is larger yet and
now Q3 is strongly driven into
saturation so VCE3,sat  0.1 V.
 For Q3 in saturation, iC3 << β iB3 . As
iB3 increases, iC3 is nearly constant
since vo = VCE3,sat and VCE3,sat goes
down from 0.2 V to 0.1 V so iC3
increases from 3.0 mA to
A,B
vCE
Ch 11 Bipolar Digital Pt. 2
iC3 = (5V - 0.1)/1.6K = 3.06 mA.
8
Simplified TTL Transfer Characteristic
VCC = 5V
VCC = 5V
RC =
1.6K
R=4K
VBE1
*
+
vo
+ +
VBC1
+
+
VBE3
vi
*
Noise Margin (Low state)
 VOL = VCE3,sat = 0.1 V
 VIL = 0.6 V
 NML = VIL - VOL = 0.6V - 0.1 V = 0.5 V
Noise Margin (High state)
 VOH = VCC = 5 V
 VIH = 0.7 V
 NMH = VOH - VIH = 5 V - 0.7 V = 4.3 V
vo
A
B
iC
VCC = 5V
NML =
VIL - VOL
0.2V
VOL = 0.1V
I
D
II III
NMH = VOH - VIH
C
0.6V 0.7V
VOL VIL VIH
ECES 352 Winter 2007
Saturation
iC/iB < β
.
C
Q3
active
D
5V
vi
VOH
Ch 11 Bipolar Digital Pt. 2
A,B
vCE
9
Simplified TTL Propagation Delay
*
VCC = 5 V

vo
iRc
RC =
1.6K
Output going high

iCap

VCC
+
+
vo
C
VCE
+
VBE
A B
VOL
=0.1V
t
vo
dvo
V v
 iRc  CC o
dt
RC
t
dvo
1

dt

V  vo RC C 0
VCE ,sat CC
t
t
t
t








RC C
RC C
RC C
RC C
vo  VCC 1  e
 5V 1  e
  VCE , sat e
  0.1V e




vo
VOH
= 5V
iCap  C
VCE,sat
tPLH
Transistor Q3 turned off (cutoff)
Charging current flows through RC
tPLH is time it takes the output to
rise from VOL = VCE,sat = 0.1 V to
1/2(VOH + VOL) = 2.6 V
t PLH  time for output to rise to
1
VOH  VOL   1 5V  0.1V   2.6V
2
2
t PLH
t

 PLH


RC C
R C
2.6V  5V 1  e
  0.1V e C


vo 
I
II III
C
0.6 V 0.7V
VIL VIH
ECES 352 Winter 2007
D
5V
vi
t PLH
RC C
5  2.6
 0.5
4.9
For R C  1.6K and C  10pF we get

e

t PLH  RC C ln 2  1.6 K (10 pF )  1.6 x10 8 sec  16 n sec
Ch 11 Bipolar Digital Pt. 2
10
Simplified TTL Propagation Delay
VCC = 5 V
vo
iRc
RC =
1.6K
*
Output going low

iCap
VCC
+

+
vo
C 2.6 V

VCE
+
VBE
VCE,sat
tPHL
Transistor Q3 turned on (initially active,
moving toward saturation) and providing
discharge current (P R  S)
But current also flows through RC
tPHL is time it takes the output to fall
from VOH = VCC = 5 V to
1/2(VOH + VOL) = 2.6 V
t
iC
vo
A B
VOH
= 5V
I
II III
S
VOL
=0.1V
C
0.6 V 0.7V
VIL VIH
R
D
5V
vi
P
vCE
ECES 352 Winter 2007
Ch 11 Bipolar Digital Pt. 2
11
Simplified TTL Propagation Delay
*
iRc
iC
+
+
VBE
iCap  C
vo
VCC = 5 V
RC =
1.6K
Output going low
VCE
vo
iCap
so
VCC
+
vo
dvo
V  vo
 iRc  iC  CC
 iC
dt
RC
t

VOH
VCC
dvo
1

dt
 vo  iC RC RC C 0
Assuming a constant transistor current, then
C 2.6 V
vo  VCC
VCE,sat
t
tPHL
t 
t



RC C
RC C
  VOH e
 iC RC 1  e




t 
t



RC C
RC C
  5V e
 (5V  iC RC ) 1  e




t PHL  time for output to fall from VOH  5V to vo  2.6V
iC
t
t

 PHL 
 PHL
R
C
C
  5V e RC C
2.6V  (5V  iC RC ) 1  e




S
2.6V  (5V  iC RC )  iC RC e
R

e
P
t PHL
RC C


t PHL
RC C
 i R

iC RC  2.4
so t PHL  RC C ln  C C 
iC RC
 iC RC  2.4 
What current to use for the transistor Q3?
vCE
ECES 352 Winter 2007
Ch 11 Bipolar Digital Pt. 2
12
Simplified TTL Propagation Delay
*
vo
VCC = 5V
iR
RC =
1.6K
iB3
+
Output going low
 Q3 starts in active mode at Pt. R
iRc
iC3
+
iCap
+
vo
VCC  VBC1  VBE 3 5V  0.7V  0.7V

 0.9 mA
R
4K
For a   50, then for the transist or in the active mode
iB 3  iR 
VCC
iC 3   iB 3  50(0.9 mA)  45 mA
C
For R C  1.6K and C  10pF we get
VCE
VBE
 45mA(1.6 K ) 
t PHL  RC C ln 
 5.5 x1010 sec  0.55 n sec

 45mA(1.6 K )  2.4 
1
t P  16 n sec  0.55 n sec  8.3 n sec
2
VCE,sat
t


iC
S

Final note:
 iC = 45 mA is a very large current,
which is useful for discharging the
capacitor quickly.
 When the capacitor is discharged, this
iC3 drops dramatically in size to only
R
iC 3 
 At this point, Q3 is now in saturation
mode since iC 3 3 mA
P
vCE
ECES 352 Winter 2007
VCC  VCE , sat 5 V  0.2 V

 3 mA
RC
1.6 K
Ch 11 Bipolar Digital Pt. 2
iB3

0.9 mA
 3.33    50
13
Simplified TTL Power Dissipation
*
Output High State
 Transistor Q3 is in cutoff so iC3 = 0, so no static
power dissipation in Q3.
 Transistor Q1 is in saturation with iB1 = iR = 1 mA
 Static power dissipation for high state,
PL1 =VCC iR = (5 V)(1 mA) = 5 mW
 So static power dissipation for the inverter for the
high output state is PH = 5 mW
*
Output Low State
 Transistor Q3 is in saturation so v o = VCE,sat = 0.1 V.
 iC3 = (VCC - VCE3,sat )/RC = (5V - 0.1 V)/1.6K = 3 mA.
 PL3 =VCC iC3 = (5 V)(3 mA) = 15 mW
 Transistor Q1 is in the inverse active mode, but still
has a large base current of 0.9 mA.
 PL1 =VCC iR = (5 V)(0.9 mA) = 4.5 mW
 Total power dissipation in low state PL =19.5 mW
 Average P = 1/2(PH + PL) = 12.3 mW
*
Power - Delay Product
 DP = P tp =(12.3 mW)(8.3 nsec) = 102 pJ
VCC = 5 V
iCap
RC =
1.6K
iR
iC3
+
+
+
vo
C
VCE
VBE
vo
A B
VOH
= 5V
VOL
=0.1V
I
II III
C
0.6 V 0.7V
VIL VIH
ECES 352 Winter 2007
D
5V
vi
Ch 11 Bipolar Digital Pt. 2
14
Simplified Transistor - Transistor Logic
*
•
* Simplified TTL very similar to RTL in
noise margins.
* Better speed due to smaller RC
used in simplified TTL (1.6 K) versus
10 K in RTL.
* Simplified TTL worse in power
dissipation and power-delay product.
* Also more costly and complex due to
use of more transistors per gate.
ECES 352 Winter 2007
*
*
Simplified TTL provides performance
similar to RTL.
Logic levels and noise margins
 Noise Margin for Low State
 NML = VIL – VO
= 0.6 V - 0.1 V = 0.5 V
 Noise Margin for High State
 NMH = VOH - VIH
= 5 V - 0.7 V = 4.3 V
 Unequal noise margins for high
and low states.
Propagation delays
 Output going low t PHL  0.55 n sec
 Output going high t PLH  16 n sec
t P  8.3 n sec
 Propagation delay
Power – Delay Product
DP  t P P  8.3 n sec 12.3mW   102 pJ
Ch 11 Bipolar Digital Pt. 2
15
Simplified TTL vs. RTL
vo
vo
vi
vi
*
Logic levels and noise margins

Noise Margin for Low State
 NML = VIL – VO = 0.6 V - 0.1 V = 0.5V

Noise Margin for High State
 NMH = VOH - VIH = 5 V - 0.7 V = 4.3 V

Unequal noise margins for high and low states.
*
Logic levels and noise margins

Noise Margin for Low State
 NML = VIL – VO = 0.7 V - 0.2 V = 0.5 V

Noise Margin for High State
 NMH = VOH - VIH = 5 V - 0.8 V = 4.2 V

Unequal noise margins for high and low states.
*
Propagation delays

Output going low

Output going high

Propagation delay
*
Propagation delays

Output going low

Output going high

Propagation delay
*
Power – Delay Product
t PHL  0.55 n sec
t PLH  16 n sec
t P  8.3 n sec
*
Power – Delay Product
t P  56 n sec

DP  t P P  56 n sec 1.2mW   67 pJ
DP  t P P  8.3 n sec 12.3mW   102 pJ
ECES 352 Winter 2007

t PHL  12 n sec
t PLH  100 n sec
Ch 11 Bipolar Digital Pt. 2
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