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Lesson 4: “Just like LEGO” The NAND gate “Reading” CMOS gates Designing CMOS gates Logic NAND 2-inputs NAND “Gates are inverters in disguise!” A B Y A 0 0 1 1 B 0 1 0 1 Paulo Moreira Y 1 1 1 0 Gates 3 NAND 3-inputs NAND 3 inputs p p Y A n B n C n Paulo Moreira Gates Pull down <=> 3 on Pull up <=> 1 on p "Delay equivalent" inverter p n/3 4 NAND 3-inputs NAND 3 inputs p p p Y n A Use transistors close to the output for critical signals Bulk effect B n C n Paulo Moreira Gates Stray capacitance 5 NAND: Switching Time, Propagation Delay tLow2High= Rp/N (N*Cout,p+Cout,n/N+Cload) tHigh2Low= N*Rn (Cout,n/N+N*Cout,p+Cload) Gate Delay=1/2*(tL2H+ tH2L) n,p : n-channel, p-channel transistors. Rp,Rn: Ron of respective transistors. N = number of Inputs. Estimation of Gate Delay: Gate Delay = K1(pSec) +K2 (pSec*um/fF)* Cload / Wn Wn=Width of n-channel FET (Wp/Wn=constant) K1 & K2 determined from spice simulation of cascaded inverters. Wp/Wn K1 K2 1 39 12.8 2 38 8.78 3 41 6.35 When FETs in series, the effective W is respectively smaller. Cload calculated from Fan-out * Capacity(per Gate) + Capacity of Line. NAND 3-inputs Bad: high stray capacitance and large area A B C Good: minimum stray capacitace and small area Shared source/drain diffusions Paulo Moreira Gates Minimum distance 8 NAND 3-inputs Paulo Moreira Gates 9 “Reading” CMOS gates (A+B) B Pull up A (A+B) (C+D) C (AB)(CD) AB+CD (C+D) D Y The NMOS pull-down => inversion Pull down NMOS activated by "1" PMOS activated by "0" AOI Paulo Moreira A C (AB) AB + CD B D AB + CD (CD) Gates 10 Designing CMOS gates Compound gate Pull up A D AB 00 01 11 10 00 1 1 1 1 CD 01 1 0 0 0 11 0 0 0 0 01 1 1 1 1 D+ABC B C Y Y = D (A + B + C) Y Pull down NMOS activated by "1" PMOS activated by "0" Y AB 00 01 11 10 D 00 1 1 1 1 CD 01 1 0 0 0 11 0 0 0 0 01 1 1 1 1 D (A + B + C) A Paulo Moreira B C Gates 11 Complex CMOS gates • Can a compound gate be arbitrarily complex? – NO, propagation delay is a strong function of fan-in: t p a0 FO a1 FI a2 FI 2 – FO Fan-out, number of loads connected to the gate: • 2 gate capacitances per FO + interconnect – FI Fan-in, Number of inputs in the gate: • Quadratic dependency on FI due to: – Resistance increase – Capacitance increase – Avoid large FI gates (Typically FI 4) Paulo Moreira Gates 12 NAND: Switching Point VSP=(n / (N*p))^1/2*VT,n+(VDD-VT,p) -------------------------------------1+(n / (N*p))^1/2 N = number of Inputs. n,p : n-channel, p-channel transistors.