Download Chapter # 4: Programmable and Steering Logic

Introduction
Chapter # 4: Programmable and
Steering Logic
4-1
Chapter Overview
Introduction
• PALs and PLAs
• Non-Gate Logic
Switch Logic
Multiplexers/Selecters and Decoders
Tri-State Gates/Open Collector Gates
ROM
• Combinational Logic Design Problems
Seven Segment Display Decoder
Process Line Controller
Logical Function Unit
Barrel Shifter
4-2
PALs and PLAs
Introduction
Pre-fabricated building block of many AND/OR gates (or NOR, NAND)
"Personalized" by making or breaking connections among the gates
Programmable Array Block Diagram for Sum of Products Form
Inputs
Dense array of
AND gates
Product
terms
Dense array of
OR gates
Outputs
4-3
PALs and PLAs
Key to Success: Shared Product Terms
Introduction
Equations
Example:
F0 = A + B' C'
F1 = A C' + A B
F2 = B' C' + A B
F3 = B' C + A
Personality Matrix
Product
term
AB
BC
AC
BC
A
Inputs
A B C
1 1 - 0 1
1 - 0
- 0 0
1 - -
Outputs
F0 F1 F2 F3
0 1 1 0
0 0 0 1
0 1 0 0
1 0 1 0
1 0 0 1
Input Side:
1 = asserted in term
0 = negated in term
- = does not participate
Output Side:
1 = term connected to output
Reus e
0 = no connection to output
of
terms
4-4
Introduction
PALs and PLAs
Example Continued
A B C
All possible connections are available
before programming
F1
F2
F3
F4
4-5
Introduction
PALs and PLAs
Example Continued
A
B
C
Unwanted connections are "blown"
AB
/BC
A/C
/B/C
AC
Note: some array structures
work by making connections
rather than breaking them
F0
F1
F2
F3
4-6
PALs and PLAs
Introduction
Alternative representation for high fan-in structures
Short-hand notation
so we don't have to
draw all the wires!
A B C D
AB
/A/B
C/D
Notation for implementing
F0 = A B + A' B'
F1 = C D' + C' D
/CD
AB+/A/B
C/D+/CD
4-7
PALs and PLAs
Design Example
Introduction
A BC
Multiple functions of A, B, C
ABC
A
F1 = A B C
B
F2 = A + B + C
C
A
F3 = A B C
B
F4 = A + B + C
C
F5 = A xor B xor C
ABC
ABC
F6 = A xor B xor C
ABC
ABC
ABC
ABC
ABC
F1
F2
F3
F4 F5
F6
4-8
PALs and PLAs
Introduction
What is difference between Programmable Array Logic (PAL) and
Programmable Logic Array (PLA)?
PAL concept : implemented by Monolithic Memories
(substrate is active materialsuch as semiconductor silicon)
programmable AND array but constrained topology of the OR Array
connections between product terms are hardwired
the higher the OR gate fanins, the fewer the functional outputs from
PAL
A given column of the OR array
has access to only a subset of
the possible product terms
PLA concept : generalized topologies in AND and OR planes
take advantage of shared product terms
slower
4-9
PALs and PLAs
Introduction
Design Example: BCD to Gray Code Converter
Truth Table
A
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
B
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
C
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
D
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
W
0
0
0
0
0
1
1
1
1
1
X
X
X
X
X
X
X
0
0
0
0
1
1
0
0
0
0
X
X
X
X
X
X
K-maps
Y
0
0
1
1
1
1
1
1
0
0
X
X
X
X
X
X
Z
0
1
1
0
0
0
0
1
1
0
X
X
X
X
X
X
A
AB
00
01
11
10
00
0
0
X
1
01
0
1
X
1
11
0
1
X
X
10
0
1
X
X
CD
A
AB
00
01
11
10
00
0
1
X
0
01
0
1
X
0
11
0
0
X
X
10
0
0
X
X
CD
D
C
C
B
B
K-map for W
K-map for X
A
AB
A
AB
00
01
11
10
00
0
1
X
0
01
0
1
X
0
11
1
1
X
X
CD
Minimized Functions:
D
00
01
11
10
00
0
0
X
1
01
1
0
X
0
11
0
1
X
X
10
1
0
X
X
CD
D
C
W=A+BD+BC
X = B C'
Y=B+C
Z = A'B'C'D + B C D + A D' + B' C D'
D
C
10
1
1
X
X
B
B
K-map for Y
K-map for Z
4-10
PALs and PLAs
Programmed PAL:
Introduction
ABCD
A
BD
BC
0
B/C
0
0
0
B
C
0
0
ABCD
BCD
A/D
BC/D
4 product terms per each OR gate
W X Y Z
4-11
PALs and PLAs
Introduction
Code Converter Discrete Gate Implementation
A
\A
1
B
D
2
B
C
3
\A
\B
\C
D
W
B
C
D
2
A
D
B
C
22
1
1
1
X
\C
B
2
1
\B
Y
4
3
4 4
Z
5
\D
\B
C
\D
3
1: 7404 hex inverters
2,5: 7400 quad 2-input NAND
3: 7410 tri 3-input NAND
4: 7420 dual 4-input NAND
4 SSI Packages vs. 1 PLA/PAL Package!
4-12
PALs and PLAs
Introduction
Another Example: Magnitude Comparator
AB=CD ABCD AB<CD AB>CD
A
AB
CD
00
A
AB
00
01
11
10
1
0
0
0
CD
00
A B C D
00
01
11
10
0
1
1
1
ABCD
ABCD
01
0
1
0
0
01
1
0
1
1
D
11
0
0
1
0
C
ABCD
D
11
1
1
0
1
10
1
1
1
0
ABCD
C
10
0
0
0
1
AC
B
B
K-map for EQ
K-map for NE
AC
BD
A
AB
AB
00
01
11
10
00
0
0
0
0
01
1
0
0
0
CD
A
01
11
10
00
0
1
1
1
ABD
01
0
0
1
1
BCD
D
11
1
1
0
1
10
1
1
0
0
C
BD
00
CD
D
11
0
0
0
0
ABC
10
0
0
1
0
BCD
C
B
B
K-map for LT
K-map for GT
EQ NE LT
GT
4-13
Non-Gate Logic
Introduction
Introduction
AND-OR-Invert
PAL/PLA
Generalized Building Blocks
Beyond Simple Gates
Kinds of "Non-gate logic":
• switching circuits built from CMOS transmission gates
• multiplexer/selecter functions
• decoders
• tri-state and open collector gates
• read-only memories
4-14
Steering Logic: Switches
Introduction
Voltage Controlled Switches
Gate
Channel
Region
Oxide
Source
Drain
Silicon Bulk
n-type Si
p-type Si
"n-Channel MOS"
Metal Gate, Oxide, Silicon Sandwich
Diffusion regions: negatively charged ions driven into Si
surface
Si Bulk: positively charged ions
4-15
Steering Logic
Introduction
Voltage Controlled Switches
Gate
Drain
Sour ce
Logic 1 on gate,
Source and Drain connected
nMOS Transistor
Gate
Sour ce
Drain
Logic 0 on gate,
Source and Drain connected
pMOS Transistor
4-16
Steering Logic
Introduction
Logic Gates from Switches
+5V
A
B
A
+5V
A
B
+5V
AB
A
A +B
Inverter
NAND Gate
NOR Gate
Pull-up network constructed from pMOS
transistors
Pull-down network constructed from nMOS
transistors
4-17
Steering Logic
Introduction
Inverter Operation
+5V
"1"
+5V
"0"
Input is 1
Pull-up does not conduct
Pull-down conducts
Output connected to GND
"0"
"1"
Input is 0
Pull-up conducts
Pull-down does not conduct
Output connected to VDD
4-18
Steering Logic
Introduction
NAND Gate Operation
"1"
"0"
"1"
+5V
"1"
+5V
"0"
A = 1, B = 1
Pull-up network does not conduct
Pull-down network conducts
Output node connected to GND
"1"
A = 0, B = 1
Pull-up network has path to VDD
Pull-down network path broken
Output node connected to VDD
4-19
Steering Logic
Introduction
NOR Gate Operation
"0"
+5V
"1"
"0"
+5V
"1"
A = 0, B = 0
Pull-up network conducts
Pull-down network broken
Output node at VDD
"0"
"0"
A = 1, B = 0
Pull-up network broken
Pull-down network conducts
Output node at GND
4-20
Steering Logic
Introduction
CMOS Transmission Gate
nMOS transistors good at passing 0's but bad at passing 1's
produce weak 1
pMOS transistors good at passing 1's but bad at passing 0's
produce weak 0
perfect "transmission" gate places these in parallel:
Control
Control
In
Out
Control
Switches
In
Control
Out
Control
Transistors
In
Out
Control
Transmission or
"Butterfly" Gate
4-21
Steering Logic
Introduction
Selection Function/Demultiplexer Function with Transmission Gates
S
Selector:
Choose I0 if S = 0
Choose I1 if S = 1
I
0
S
I
Z
S
1
S
S
Demultiplexer:
I to Z0 if S = 0
I to Z1 if S = 1
Z0
I
S
S
Z1
S
4-22
Steering Logic
Introduction
Use of Multiplexer/Demultiplexer in Digital Systems
A
Demultiplexers
Y
Multiplexers
B
Z
A
Y
Demultiplexers
B
Multiplexers
Z
So far, we've only seen point-to-point connections among gates
Mux/Demux used to implement multiple source/multiple destination
interconnect
4-23
Steering Logic
Well-formed Switching Networks
Introduction
Problem with the Demux implementation:
multiple outputs, but only one connected to the input!
S
Z0
S
"0"
I
S
S
Z1
S
"0"
S
The fix: additional logic to drive every output to a known value
Never allow outputs to "float"
4-24
Steering Logic
Introduction
Complex Steering Logic Example
N Input Tally Circuit: count # of 1's in the inputs
I
1
0
1
I1
Zero
One
I1
Straight Through
1
0
0
1
I1
"0"
Zero
One
"0"
One
"1"
Zero
Diagonal
"0"
One
Conventional Logic
for 1 Input Tally
Function
"1"
Zero
"0"
Switch Logic Implementation
of Tally Function
4-25
Steering Logic
Introduction
Complex Steering Logic Example
Operation of the 1 Input Tally Circuit
"0"
"0"
One
"0"
"0"
One
"1"
Zero
"0"
"1"
Zero
"0"
Input is 0, straight through switches enabled
4-26
Steering Logic
Introduction
Complex Steering Logic Example
Operation of 1 input Tally Circuit
"1"
"0"
"1"
On e
Zero
"1"
"0"
On e
"1"
Zero
"0"
"0"
Input = 1, diagonal switches enabled
4-27
Steering Logic
Introduction
Complex Steering Logic Example
Extension to the 2-input case
I 1 I2
0
0
1
1
0
1
0
1
Zero One Two
1
0
0
0
0
1
1
0
0
0
0
1
I1
I2
Zero
One
Two
Conventional logic implementation
4-28
Steering Logic
Introduction
Complex Steering Logic Example
Switch Logic Implementation: 2-input Tally Circuit
I2
I2
I1
"0"
Tw o
"0"
"1"
"0"
"0"
One
Ze ro
Tw o
One
Ze ro
"0"
I1
"0"
One
One
Cascade the 1-input implementation!
"1"
"0"
Ze ro
Ze ro
"0"
4-29
Steering Logic
Introduction
Complex Steering Logic Example
Operation of 2-input implementation
"0"
"0"
"0"
"0"
"1"
"0"
"0"
One
"1"
"0"
"0"
Zero
"1"
"0"
"1"
"0"
"0"
"1"
"0"
"0"
"1"
"0"
"0"
One
Zero
"0"
"0"
One
Zero
"0"
"1"
"0"
"0"
"1"
"0"
"1"
"1"
"0"
"0"
"1"
"0"
"0"
One
Zero
"1"
"0"
"0"
"0"
4-30
Introduction
Multiplexers/Selectors
Use of Multiplexers/Selectors
Multi-point connections
A0
Sa
A1
B0
B1
MUX
MUX
A
B
Multiple input sources
Sb
Sum
Ss
DEMUX
S0
Multiple output destinations
S1
4-31
Introduction
Multiplexers/Selectors
General Concept
2
n
data inputs, n control inputs, 1 output
n
used to connect 2 points to a single point
control signal pattern form binary index of input connected to output
Z = A' I 0 + A I 1
A
0
1
Functional form
Logical form
Z
I0
I1
I1
0
0
0
0
1
1
1
1
I0
0
0
1
1
0
0
1
1
A
0
1
0
1
0
1
0
1
Z
0
0
1
0
0
1
1
1
Two alternative forms
for a 2:1 Mux Truth Table
4-32
Multiplexers/Selectors
I0
2:1
mux
I1
Introduction
Z = A' I 0 + A I 1
Z
A
I0
I1
I2
I3
4:1
mux
A
I0
I1
I2
I3
Z
B
8:1
mux
I4
I5
I6
I7
A
Z = A' B' I0 + A' B I1 + A B' I2 + A B I3
B
Z
C
Z = A' B' C' I0 + A' B' C I1 + A' B C' I2 + A' B C I3 +
A B' C' I4 + A B' C I5 + A B C' I6 + A B C I7
n -1
2
In general, Z = S
m I
k=0
k k
in minterm shorthand form for a 2 n :1 Mux
4-33
Multiplexers/Selectors
Introduction
Alternative Implementations
A
I0
B
I0
I1
Z
Z
I2
I1
I3
I2
A
B
Gate Level
Implementation
of 4:1 Mux
thirty six transistors
I3
Transmission Gate
Implementation of
4:1 Mux
twenty transistors
4-34
Multiplexer/Selector
Introduction
Large multiplexers can be implemented by cascaded smaller ones
I0
I1
I2
I3
0 4:1
1 mux
2
3 S1 S0
I4
I5
I6
I7
0 4:1
1 mux
2
3 S1 S0
B
Control signals B and C simultaneously
choose one of I0-I3 and I4-I7
8:1
mux
0 2:1
mux
1 S
Z
Control signal A chooses which of the
upper or lower MUX's output to gate to Z
I0
0
I1
1 S
C
C
A
I2
0
I3
1 S
0
1
Alternative 8:1 Mux Implementation
C
I4
0
I5
1 S
Z
2
3 S0
C
I6
0
I7
1 S
A
S1
B
C
4-35
Multiplexer/Selector
Introduction
Multiplexers/selectors as a general purpose logic block
n-1
2
:1 multiplexer can implement any function of n variables
n-1 control variables; remaining variable is a data input to the mux
Example:
F(A,B,C) = m0 + m2 + m6 + m7
= A' B' C' + A' B C' + A B C' + A B C
= A' B' (C') + A' B (C') + A B' (0) + A B (1)
1
0
1
0
0
0
1
1
0
1
2
3
4
5
6
7
F
8:1
MUX
S2 S1 S0
A
B
C
A
0
0
0
0
1
1
1
1
B
0
0
1
1
0
0
1
1
C
0
1
0
1
0
1
0
1
F
1
0
1
0
0
0
1
1
C
C
0
C
C
0
1
0
1
2
3
4:1
MUX
S1
S0
A
B
F
1
"Lookup Table"
4-36
Multiplexer/Selector
Generalization
Introduction
I 1 I 2 … In
…
n-1 Mux
control variables
single Mux
data variable
0
1
F
0
0
0
1
1
0
1
1
Four possible
configurations
of the truth table rows
0
In
In
1
Can be expressed as
a function of In, 0, 1
Example:
G(A,B,C,D) can be implemented by an 8:1 MUX:
A
AB
K-map
00
01
11
10
CD
Choose A,B,C
as control variables
00 1
0 1
1
01
1
0
0
0
11
1
1
0
1
10
0
1
1
0
C
B
Multiplexer
Implementation
TTL package efficient
May be gate inefficient
1
D
0
1
D
D
D
D
0
1
2
3
4
5
6
7
G
8:1
mux
S2
A
S1
B
S0
C
4-37
Multiplexer/Selector
Introduction
• TTL quad 2:1 multiplexers with enable
4-38
Decoders/Demultiplexers
Introduction
Decoder: single data input, n control inputs, 2
n
outputs
control inputs (called select S) represent Binary index of output to which
the input is connected
data input usually called "enable" (G)
1:2 Decoder:
O0 = G • S; O1 = G • S
2:4 Decoder:
O0 = G • S0 • S1
3:8 Decoder:
O0 = G • S0 • S1 • S2
O1 = G • S0 • S1 • S2
O2 = G • S0 • S1 •S2
O1 = G • S0 • S1
O3 = G • S0 • S1 • S2
O2 = G • S0 • S1
O4 = G • S0 • S1 • S2
O3 = G • S0 • S1
O5 = G • S0 • S1 • S2
O6 = G • S0 • S1 • S2
O7 = G • S0 • S1 • S2
4-39
Decoders/Demultiplexers
Introduction
Alternative Implementations
G
Select
/G
Output 0 Select
Output 0
Output 1
Output 1
1:2 Decoder, Active Low Enable
1:2 Decoder, Active High Enable
/G
G
Select0
Output 0
Output 0
Output 1
Output 1
Output 2
Output 2
Output 3
Output 3
Select1
2:4 Decoder, Active High Enable
Select0
Select1
2:4 Decoder, Active Low Enable
4-40
Introduction
Decoders/Demultiplexers
Switch Logic Implementations
Select
Select
G
G
Output
Select
Select
Output
0
Select
Select
0
"0"
Select
Output
1
Select
Select
Output
1
Select
Naive, Incorrect Implementation
Select
All outputs not driven at all times
"0"
Select
Correct 1:2 Decoder Implementation
4-41
Introduction
Decoders/Demultiplexers
Switch Implementation of 2:4 Decoder
Select
G
0
Select
1
Output
0
Operation of 2:4 Decoder
"0"
"0"
G
S0 = 0, S1 = 0
Output
1
"0"
one straight thru path
three diagonal paths
"0"
G
Output
2
"0"
"0"
G
Output
3
"0"
"0"
4-42
Decoder/Demultiplexer
Decoder as a Logic Building Block
Enb
3:8
dec
S2
A
S1
B
S0
0
1
2
3
4
5
6
7
ABC
ABC
ABC
ABC
ABC
ABC
ABC
ABC
Introduction
Decoder Generates Appropriate
Minterm based on Control Signals
C
Example Function:
F1 = A' B C' D + A' B' C D + A B C D
F2 = A B C' D' + A B C
F3 = (A' + B' + C' + D')
4-43
Introduction
Decoder/Demultiplexer
Decoder as a Logic Building Block
Enb
4:16
dec
S3 S2 S1 S0
A
B C
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
ABCD
AB C D
AB C D
AB C D
AB C D
AB C D
AB C D
AB C D
AB C D
AB C D
AB C D
AB C D
AB
AB
AB
AB
CD
CD
CD
CD
F1
F2
F3
D
If active low enable, then use NAND gates!
4-44