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EE4800 CMOS Digital IC Design & Analysis Lecture 4 DC and Transient Responses, Circuit Delays Zhuo Feng 4.1 Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis Outline ■ Pass Transistors ■ DC Response ■ Logic Levels and Noise Margins ■ Transient Response ■ RC Delay Models ■ Delay Estimation 4.2 Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis Activity 1) If the width of a transistor increases, the current will increase decrease not change 2) If the length of a transistor increases, the current will increase decrease not change 3) If the supply voltage of a chip increases, the maximum transistor current will increase decrease not change 4) If the width of a transistor increases, its gate capacitance will increase decrease not change 5) If the length of a transistor increases, its gate capacitance will increase decrease not change 6) If the supply voltage of a chip increases, the gate capacitance of each transistor will increase decrease not change 4.3 Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis Activity 1) If the width of a transistor increases, the current will increase decrease not change 2) If the length of a transistor increases, the current will increase decrease not change 3) If the supply voltage of a chip increases, the maximum transistor current will increase decrease not change 4) If the width of a transistor increases, its gate capacitance will increase decrease not change 5) If the length of a transistor increases, its gate capacitance will increase decrease not change 6) If the supply voltage of a chip increases, the gate capacitance of each transistor will increase decrease not change 4.4 Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis Pass Transistors ■ We have assumed source is grounded ■ What if source > 0? VDD ► e.g. pass transistor passing VDD ■ Vg = VDD VDD ► If Vs > VDD-Vt, Vgs < Vt ► Hence transistor would turn itself off ■ NMOS pass transistors pull no higher than VDD-Vtn ► Called a degraded “1” ► Approach degraded value slowly (low Ids) ■ PMOS pass transistors pull no lower than Vtp 4.5 Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis Pass Transistor Ckts VDD VDD VDD VDD VDD Vs = VDD-Vtn Vs = |Vtp| VDD-Vtn VDD-Vtn VDD VDD-Vtn VDD VSS 4.6 VDD Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis VDD-2Vtn VDD-Vtn DC Response ■ DC Response: Vout vs. Vin for a gate ■ Ex: Inverter ► When Vin = 0 -> Vout = VDD ► When Vin = VDD -> Vout = 0 VDD ► In between, Vout depends on transistor size and current Idsp Vin Vout ► By KCL, must settle such that Idsn Idsn = |Idsp| ► We could solve equations ► But graphical solution gives more insight 4.7 Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis Transistor Operation ■ Current depends on region of transistor behavior ■ For what Vin and Vout are NMOS and PMOS in ► Cutoff? ► Linear? ► Saturation? 4.8 Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis NMOS Operation Cutoff Vgsn < Vtn Linear Vgsn > Vtn Saturated Vgsn > Vtn Vdsn < Vgsn – Vtn Vdsn > Vgsn – Vtn VDD Vin Idsp Idsn 4.9 Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis Vout NMOS Operation Cutoff Vgsn < Vtn Linear Vgsn > Vtn Saturated Vgsn > Vtn Vdsn < Vgsn – Vtn Vdsn > Vgsn – Vtn VDD Vgsn = Vin Vdsn = Vout 4.10 Vin Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis Idsp Idsn Vout NMOS Operation Cutoff Vgsn < Vtn Vin < Vtn Linear Vgsn > Vtn Vin > Vtn Vdsn < Vgsn – Vtn Vout < Vin - Vtn Saturated Vgsn > Vtn Vin > Vtn Vdsn > Vgsn – Vtn Vout > Vin - Vtn VDD Vgsn = Vin Vdsn = Vout 4.11 Vin Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis Idsp Idsn Vout PMOS Operation Cutoff Linear Saturated Vgsp > Vgsp < Vgsp < Vdsp > Vdsp < VDD Vin Idsp Idsn 4.12 Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis Vout PMOS Operation Cutoff Linear Saturated Vgsp > Vtp Vgsp < Vtp Vgsp < Vtp Vdsp > Vgsp – Vtp Vdsp < Vgsp – Vtp VDD Vin Idsp Idsn 4.13 Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis Vout PMOS Operation Cutoff Linear Saturated Vgsp > Vtp Vgsp < Vtp Vgsp < Vtp Vdsp > Vgsp – Vtp Vdsp < Vgsp – Vtp VDD Vgsp = Vin - VDD Vdsp = Vout - VDD 4.14 Vtp < 0 Vin Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis Idsp Idsn Vout PMOS Operation Cutoff Vgsp > Vtp Vin > VDD + Vtp Linear Vgsp < Vtp Vin < VDD + Vtp Vdsp > Vgsp – Vtp Vout > Vin - Vtp Saturated Vgsp < Vtp Vin < VDD + Vtp Vdsp < Vgsp – Vtp Vout < Vin - Vtp VDD Vgsp = Vin - VDD Vdsp = Vout - VDD 4.15 Vtp < 0 Vin Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis Idsp Idsn Vout I-V Characteristics ■ Make PMOS is wider than NMOS such that bn = bp Vgsn5 Vgsn4 Idsn Vgsn3 -Vdsp Vgsp1 Vgsp2 -VDD 0 VDD Vdsn Vgsp3 Vgsp4 -Idsp Vgsp5 4.16 Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis Vgsn2 Vgsn1 Current vs. Vout, Vin Idsn, |Idsp| Vin0 Vin5 Vin1 Vin4 Vin2 Vin3 Vin3 Vin4 Vin2 Vin1 Vout 4.17 Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis VDD Load Line Analysis ■ For a given Vin: ► Plot Idsn, Idsp vs. Vout ► Vout must be where |currents| are equal in Idsn, |Idsp| Vin0 Vin5 Vin1 Vin4 Vin Idsp Idsn Vin2 Vin3 Vin3 Vin4 Vin2 Vin1 Vout 4.18 VDD VDD Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis Vout Load Line Analysis ■ Vin = 0 Vin0 Idsn, |Idsp| Vin0 Vout 4.19 Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis VDD Load Line Analysis ■ Vin = 0.2VDD Idsn, |Idsp| Vin1 Vin1 Vout 4.20 Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis VDD Load Line Analysis ■ Vin = 0.4VDD Idsn, |Idsp| Vin2 Vin2 Vout 4.21 Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis VDD Load Line Analysis ■ Vin = 0.6VDD Idsn, |Idsp| Vin3 Vin3 Vout 4.22 Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis VDD Load Line Analysis ■ Vin = 0.8VDD Vin4 Idsn, |Idsp| Vin4 Vout 4.23 Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis VDD Load Line Analysis ■ Vin = VDD Vin0 Idsn, |Idsp| Vin5 Vin1 Vin2 Vin3 Vin4 Vout 4.24 Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis VDD Load Line Summary Idsn, |Idsp| Vin0 Vin5 Vin1 Vin4 Vin2 Vin3 Vin3 Vin4 Vin2 Vin1 Vout 4.25 Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis VDD DC Transfer Curve ■ Transcribe points onto Vin vs. Vout plot Vin0 Vin5 VDD A Vin1 Vin4 Vin2 Vin3 Vin3 Vin4 Vin2 Vin1 Vout 4.26 VDD B Vout C D 0 Vtn Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis VDD/2 Vin E VDD+Vtp VDD Operating Regions ■ Revisit transistor operating regions Region NMOS PMOS A Cutoff Linear B Saturation Linear C Saturation Saturation D Linear Saturation E Linear Cutoff VDD A B Vout C D 0 Vtn VDD/2 Vin 4.27 Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis E VDD+Vtp VDD Beta Ratio ■ If bp / bn 1, switching point will move from VDD/2 ■ Called skewed gate ■ Other gates: collapse into equivalent inverter VDD bp 10 bn Vout 2 1 0.5 bp 0.1 bn 0 Vin 4.28 Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis VDD Noise Margins ■ How much noise can a gate input see before it does not recognize the input? Output Characteristics Logical High Output Range VDD Input Characteristics Logical High Input Range VOH NMH VIH VIL Indeterminate Region NML Logical Low Output Range VOL GND 4.29 Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis Logical Low Input Range Logic Levels ■ To maximize noise margins, select logic levels at ► unity gain point of DC transfer characteristic Vout Unity Gain Points Slope = -1 VDD VOH b p/b n > 1 Vin VOL Vin 0 Vtn 4.30 Vout VIL VIH VDD- VDD |Vtp| Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis Transient Response ■ DC analysis tells us Vout if Vin is constant ■ Transient analysis tells us Vout(t) if Vin(t) changes ► Requires solving differential equations ■ Input is usually considered to be a step or ramp ► From 0 to VDD or vice versa 4.31 Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis Inverter Step Response ■ Ex: find step response of inverter driving load cap Vin (t ) u(t t0 )VDD Vout (t t0 ) Vin(t) dVout (t ) dt 4.32 Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis Vout(t) Cload Idsn(t) Inverter Step Response ■ Ex: find step response of inverter driving load cap Vin (t ) u(t t0 )VDD Vout (t t0 ) VDD Vin(t) dVout (t ) dt 4.33 Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis Vout(t) Cload Idsn(t) Inverter Step Response ■ Ex: find step response of inverter driving load cap Vin (t ) u(t t0 )VDD Vout (t t0 ) VDD Vin(t) dVout (t ) I dsn (t ) dt Cload I dsn (t ) 4.34 Vout Vout t t0 VDD Vt VDD Vt Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis Vout(t) Cload Idsn(t) Inverter Step Response ■ Ex: find step response of inverter driving load cap Vin (t ) u(t t0 )VDD Vin(t) Vout (t t0 ) VDD dVout (t ) I dsn (t ) dt Cload 0 2 b I dsn (t ) V V DD 2 V (t ) b VDD Vt out 2 4.35 Vout(t) Cload Idsn(t) t t0 Vout VDD Vt V (t ) V V V out out DD t Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis Inverter Step Response ■ Ex: find step response of inverter driving load cap Vin (t ) u(t t0 )VDD Vout (t t0 ) VDD Vin(t) Vout(t) Cload dVout (t ) I dsn (t ) dt Cload 0 2 b I dsn (t ) V V DD 2 V (t ) b VDD Vt out 2 4.36 Idsn(t) Vin(t) t t0 Vout VDD Vt V (t ) V V V out out DD t Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis Vout(t) t0 t Delay Definitions ■ tpdr: rising propagation delay ► From input to rising output crossing VDD/2 ■ tpdf: falling propagation delay ► From input to falling output crossing VDD/2 ■ tpd: average propagation delay ► tpd = (tpdr + tpdf)/2 ■ tr: rise time ► From output crossing 0.2 VDD to 0.8 VDD ■ tf: fall time ► From output crossing 0.8 VDD to 0.2 VDD 4.37 Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis Delay Definitions ■ tcdr: rising contamination delay ► From input to rising output crossing VDD/2 ■ tcdf: falling contamination delay ► From input to falling output crossing VDD/2 ■ tcd: average contamination delay ► tpd = (tcdr + tcdf)/2 4.38 Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis Simulated Inverter Delay ■ Solving differential equations by hand is too hard ■ SPICE simulator solves the equations numerically ► Uses more accurate I-V models too! ■ But simulations take time to write 2.0 1.5 1.0 (V) Vin tpdf = 66ps tpdr = 83ps Vout 0.5 0.0 0.0 200p 400p 600p 800p t(s) 4.39 Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis 1n Delay Estimation ■ We would like to be able to easily estimate delay ► Not as accurate as simulation ► But easier to ask “What if?” ■ The step response usually looks like a 1st order RC response with a decaying exponential. ■ Use RC delay models to estimate delay ► C = total capacitance on output node ► Use effective resistance R ► So that tpd = RC ■ Characterize transistors by finding their effective R ► Depends on average current as gate switches 4.40 Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis Effective Resistance ■ Shockley models have limited value ► Not accurate enough for modern transistors ► Too complicated for much hand analysis ■ Simplification: treat transistor as resistor ► Replace Ids(Vds, Vgs) with effective resistance R ▼ Ids = Vds/R ► R averaged across switching of digital gate ■ Too inaccurate to predict current at any given time ► But good enough to predict RC delay 4.41 Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis RC Delay Model ■ Use equivalent circuits for MOS transistors ► Ideal switch + capacitance and ON resistance ► Unit NMOS has resistance R, capacitance C ► Unit PMOS has resistance 2R, capacitance C ■ Capacitance proportional to width ■ Resistance inversely proportional to width d g d k s s kC R/k 2R/k g g kC kC d k s s 4.42 kC Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis kC g kC d RC Values ■ Capacitance ► C = Cg = Cs = Cd = 2 fF/mm of gate width ► Values similar across many processes ■ Resistance ► R 6 KW*mm in 0.6um process ► Improves with shorter channel lengths ■ Unit transistors ► May refer to minimum contacted device (4/2 l) ► Or maybe 1 mm wide device ► Doesn’t matter as long as you are consistent 4.43 Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis Inverter Delay Estimate ■ Estimate the delay of a fanout-of-1 inverter 2C R A 2 Y 2 1 1 2C 2C 2C Y R C R C C Delay = 6RC 4.44 2C Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis C C Delay Model Comparison 4.45 Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis Example: 3-input NAND ■ Sketch a 3-input NAND with transistor widths chosen to achieve effective rise and fall resistances equal to a unit inverter (R). 2 2 2 3 3 3 4.46 Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis 3-input NAND Caps ■ Annotate the 3-input NAND gate with gate and diffusion capacitance. 2 2 2 3 3 3 4.47 Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis 3-input NAND Caps ■ Annotate the 3-input NAND gate with gate and diffusion capacitance. 2C 2 2C 2C 2C 2 2C 2 2C 3C 3C 3C 4.48 2C 2C 2C 3 3 3 Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis 3C 3C 3C 3C 3-input NAND Caps ■ Annotate the 3-input NAND gate with gate and diffusion capacitance. 2 2 3 5C 5C 5C 4.49 2 3 3 Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis 9C 3C 3C Elmore Delay 1v t V (t ) 1 e RC V(t) R C Time Constant=RC What is the time constant for more complex circuits? A B Inv 1 4.50 Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis C Inv 2 Elmore Delay (Cont.) ■ ON transistors look like resistors ■ Pullup or pulldown network modeled as RC ladder ■ Elmore delay of RC ladder t pd Ri to sourceCi nodes i R1C1 R1 R2 C2 ... R1 R2 ... RN CN R1 4.51 R2 R3 C1 C2 RN C3 Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis CN Elmore Delay (Cont’d) Resistance-oriented Formula: Tdelay Ri Cdownstream,i i on path Tdelay,4=R1(C1+C2+C3+C4+C5)+R2(C2+C4+C5)+R4C4 4.52 Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis Example: 2-input NAND ■ Estimate worst-case rising and falling delay of 2- input NAND driving h identical gates. 2 4.53 2 A 2 B 2x Y Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis h copies Example: 2-input NAND ■ Estimate rising and falling propagation delays of a 2-input NAND driving h identical gates. 2 2 A 2 B 2x 4.54 6C Y 4hC 2C Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis h copies Example: 2-input NAND ■ Estimate rising and falling propagation delays of a 2-input NAND driving h identical gates. 2 2 A 2 B 2x Y 4hC 6C h copies 2C Rising Delay R Y (6+4h)C t pdr 6 4h RC 4.55 Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis Example: 2-input NAND ■ Estimate rising and falling propagation delays of a 2-input NAND driving h identical gates. 2 2 A 2 B 2x 6C Y 4hC h copies 2C Falling Delay x R/2 R/2 2C Y (6+4h)C t pdf 2C R2 6 4h C R2 R2 7 4h RC 4.56 Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis Delay Components ■ Delay has two parts ► Parasitic delay ▼ 6 or 7 RC ▼ Independent of load ► Effort delay ▼ 4h RC ▼ Proportional to load capacitance 4.57 Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis Contamination Delay ■ Best-case (contamination) delay can be substantially less than propagation delay. ■ Ex: If both inputs fall simultaneously 2 2 A 2 B 2x R R Y (6+4h)C 4.58 6C Y 4hC 2C tcdr 3 2h RC Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis Diffusion Capacitance ■ We assumed contacted diffusion on every s / d. ■ Good layout minimizes diffusion area ■ Ex: NAND3 layout shares one diffusion contact ► Reduces output capacitance by 2C ► Merged un-contacted diffusion might help too 2C Shared Contacted Diffusion 2C Isolated Contacted Diffusion Merged Uncontacted Diffusion 2 2 3 3 3C 3C 3C 4.59 2 Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis 3 7C 3C 3C Layout Comparison ■ Which layout is better? VDD A VDD B Y GND 4.60 A B Y GND Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis
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