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CMOS processes in the 100 nm minimum
feature size range for applications to the next
generation collider experiments
L. Rattia,c, M. Manghisonib,c, V. Reb,c,
V. Spezialia,c, G. Traversib,c
aUniversità
degli Studi di Pavia
Dipartimento di Elettronica
bUniversità
degli Studi di Bergamo
Dipartimento di Ingegneria Industriale
cINFN
Sezione di Pavia
Motivation
Use of CMOS microelectronic processes in the last two decades has had a deep
impact on the way HEP instrumentation is conceived
Quarter micron technology able to comply with the challenging design
requirements of the LHC experiments in terms of
noise figure
power dissipation
radiation tolerance
Luminosity and track densities expected at the next generation colliders (LHC
upgrade, ILC, Super B-Factory) set the demand for increased spatial
resolution, denser functional packing, higher radiation hardness and better
noise/power trade-off
HEP people is considering moving to more scaled CMOS processes
Technology monitoring to
keep design criteria and methodologies up to date
fight process obsolescence
study scaling down effects on the main design parameters
VI International Meeting on Front-End Electronics, Perugia, May 18th 2006
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Investigated technologies and devices
Single transistors from HCMOS9 130 nm and CMOS090 90 nm triple well,
epitaxial CMOS technologies by STMicroelectronics
HCMOS9 (Lmin=130 nm)
CMOS090 (Lmin=90 nm)
Technology features:
– VDD = 1.2 V
– tOX= 2 nm
– COX=15 fF/μm2
Technology features:
– VDD = 1 V
– tOX= 1.6 nm
– COX=18 fF/μm2
Available geometries
– W = 200, 600, 1000 μm
– L = 0.13 - 1 μm
Available geometries
– W = 100, 200, 600, 1000 μm
– L = 0.1 – 0.7 μm
Devices under test are PMOS and NMOS transistors with standard
open layout
VI International Meeting on Front-End Electronics, Perugia, May 18th 2006
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Operating region
Drain current in DUTs: from tens of mA to 1 mA  low power operation as in high
density front-end circuits
100
Strong inversion law
Weak inversion law
m D
g /I [1/V]
NMOS
PMOS
10
CMOS 90 nm
CMOS 130 nm
*
I
1
-9
10
10
-8
10
-7
I L/W [A]
D
*
*
I
Z,P,130
I
Z,P,90
10
I*Z  2mCOXnVT2
Z,N,90
-6
10
*
I
Z,N,130
Characteristic normalized drain current I*Z may
provide a reference point to define device operating
region
-5
• μ carrier mobility
• COX specific gate oxide
capacitance
• VT thermal voltage
• n proportional to ID(VGS)
subthreshold characteristic
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Operating region
Inversion coefficient
100
10
IC 0 
Moderate inversion
1
ID
W
I*Z
L
At the considered drain currents, DUTs work
in weak or moderate inversion region
0.1
0.01
0.1
Weak inversion
90 nm tech
W=600 mm
10
90 nm
-6
130 nm
1
180 nm
Drain Current [mA]
z
*
At a given drain current, operation
is shifted towards weak inversion
region with technology scaling
I [A]
Inversion Coefficeint
Strong inversion
nmos L=0.13 mm
nmos L=1.00 mm
pmos L=0.13 mm
pmos L=1.00 mm
10
-7
NMOS
PMOS
1
1.5
STMicroelectronics
2.5
2
Physical t
OX
3.5
3
[nm]
VI International Meeting on Front-End Electronics, Perugia, May 18th 2006
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Transconductance
0.03
0.03
L=0.13 mm
90 nm tech
L=0.70 mm
NMOS
Transconductance [A/V]
Transconductance [A/V]
L=0.35 mm
0.02
90 nm tech
W=600 mm
|V |=0.6 V
DS
0.01
130 nm tech
0.02
NMOS
W=600 mm
V =0.6 V
L=0.35 mm
DS
0.01
PMOS
0
0
0
0.0002
0.0004
0.0006
Drain Current [A]
0.0008
0.001
0
0.0002
0.0004
0.0006
0.0008
0.001
Drain Current [A]
At small ID (weak inversion), gm fairly independent of the device
dimension and polarity
gm 
ID
nVT
In weak inversion, possible difference between PMOS and NMOS and between CMOS
nodes only due to different n values (n1.25 for both polarities and technologies
considered here)
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Noise in CMOS transistors
Noise in the drain current of a MOSFET can be represented through an
equivalent noise voltage source in series with the device gate
2
S2V (f)  S2W  S1/f
(f)
SW - white noise
• channel thermal noise (main
contribution in the considered
operating conditions)
4k T
S  B ,
gm
• kB Boltzmann’s constant
   W n
• γ channel thermal noise
coefficient
2
ch
• T absolute temperature
S1/f - 1/f noise
• technology dependent contribution
2
S1/f
(f) 
kf
COX WLf  f
• kf 1/f noise parameter
• αf 1/f noise slope-related
coefficient
• αw excess noise coefficient
• other contributions from parasitic
resistances
• both kf and αf depends on the polarity
of the DUT
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Noise in different CMOS generations
Noise Voltage Spectrum [nV/Hz 1/2]
100
W/L = 2000/0.45, 0.25 um process
W/L = 1000/0.5, 0.13 um process
W/L = 600/0.5, 0.09 um process
250 nm TSMC
C = 6 pF
IN
10
130 nm STM
I = 100 mA
90 nm STM
D
NMOS
1
103
104
105
106
107
108
Frequency [Hz]
VI International Meeting on Front-End Electronics, Perugia, May 18th 2006
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NMOS
L=0.13 mm
1/2
100
Noise Voltage Spectrum [nV/Hz ]
1/2
Noise Voltage Spectrum [nV/Hz ]
Noise vs gate length – STM 130 nm
L=0.35 mm
L=1.00 mm
10
130 nm tech
W=1000 mm
I =0.25 mA
1
D
V =600 mV
100
PMOS
L=0.35 mm
L=1.00 mm
10
130 nm tech
W=1000 mm
I =0.25 mA
1
D
|V |=600 mV
DS
3
10
L=0.13 mm
DS
4
10
10
5
6
10
Frequency [Hz]
10
7
8
10
2
10
3
10
10
4
5
10
10
6
10
7
8
10
Frequency [Hz]
High frequency, white noise virtually independent of the gate length L, in
agreement with gm behavior
1/f noise contribution decreases with increasing channel length, as predicted by the
noise equation
VI International Meeting on Front-End Electronics, Perugia, May 18th 2006
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Noise vs drain current - NMOS
STM 130 nm
Noise Voltage Spectrum [nV/Hz ]
100
Id=0.10 mA
Id=0.25 mA
Id=1.00 mA
10
1
NMOS
W/L=1000/0.35
V =600 mV
DS
0.1
3
10
4
10
10
5
6
10
Frequency [Hz]
10
7
STM 90 nm
1/2
1/2
Noise Voltage Spectrum [nV/Hz ]
100
8
10
Id=0.10 mA
Id=0.25 mA
Id=1.00 mA
10
1
NMOS
W/L=600/0.2
V =600 mV
DS
0.1
3
10
4
10
10
5
6
10
7
10
Frequency [Hz]
High frequency, white noise decreases with increasing drain current in both
technologies, in agreement with gm behavior
1/f noise contribution is to a large extent independent of the drain current
VI International Meeting on Front-End Electronics, Perugia, May 18th 2006
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Noise vs drain current - PMOS
STM 130 nm
Noise Voltage Spectrum [nV/Hz ]
100
Id=0.10 mA
Id=0.25 mA
Id=1.00 mA
10
1
PMOS
W/L=1000/0.35
|V |=600 mV
DS
0.1
2
10
3
10
10
4
5
10
Frequency [Hz]
10
6
STM 90 nm
1/2
1/2
Noise Voltage Spectrum [nV/Hz ]
100
7
10
Id=0.10 mA
Id=0.25 mA
Id=1.00 mA
10
1
PMOS
W/L=600/0.2
|V |=600 mV
DS
0.1
2
10
3
10
10
4
5
10
10
6
7
10
Frequency [Hz]
High frequency, white noise decreases with increasing drain current, more
markedly so in the 90 nm technology
1/f noise contribution increases with increasing current, more significantly in the
STM 130 nm technology
VI International Meeting on Front-End Electronics, Perugia, May 18th 2006
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100
1/2
Noise Voltage Spectrum [nV/Hz ]
1/2
Noise Voltage Spectrum [nV/Hz ]
Noise and inversion region
STM 90 nm
STM 130 nm
10
NMOS
W/L=600/0.35
I =0.1 mA
1
D
V =600 mV
100
STM 90 nm
STM 130 nm
10
NMOS
W/L=600/0.35
I =1 mA
1
D
V =600 mV
DS
3
10
4
10
DS
10
5
6
10
Frequency [Hz]
10
7
8
10
3
10
4
10
10
5
6
10
10
7
8
10
Frequency [Hz]
At low drain current both devices work in the weak inversion region  channel
thermal noise is roughly the same for both devices
At high drain current, a significant difference in the channel thermal noise can be
detected  device from the 90 nm technology works closer to weak inversion region
Better 1/f noise performance provided by the STM 90 nm technology
VI International Meeting on Front-End Electronics, Perugia, May 18th 2006
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Channel thermal noise – STM 90 nm
Equivalent Noise Resistance [
300
Equivalent channel thermal noise
resistance
90 nm tech
NMOS L>0.13 mm
Linear fit
offset = 1.68 +/- 1.45
slope = 0.96 +/- 0.02
250
200
R Th
S2W

4k B T
150
slope  excess noise coefficient w
100
offset  noise contributions from
parasitic resistors
50
0
0
50
100
150
200
250
300
n/g [
m
w close to unity  no sizeable short channel effects in the considered operating
regions (no data available for channel thermal noise in devices with L ≤0.13 mm)
Negligible contributions from parasitic resistances
VI International Meeting on Front-End Electronics, Perugia, May 18th 2006
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Channel thermal noise – STM 130 nm
300
Equivalent Noise Resistance [
Equivalent Noise Resistance [
300
250
200
150
100
130 nm tech
NMOS L > 0.13 mm
Linear fit
offset = 6.85 +/- 1.90
slope = 1.01 +/- 0.02
50
130 nm tech
PMOS
Linear fit
offset = 1.82 +/- 2.12
slope = 0.97 +/- 0.02
250
200
150
100
50
0
0
0
50
100
150
n/g [
m
200
250
300
0
50
100
150
200
250
n/g [
m
αw close to unity  no sizeable short channel effects in the considered operating
regions also for STM 130 nm technology (except for NMOS with L=0.13 mm)
Negligible contributions from parasitic resistances in NMOS devices, larger in PMOS
transistors  possibly due to different doping levels used in critical layers
VI International Meeting on Front-End Electronics, Perugia, May 18th 2006
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300
Flicker noise
90 nm tech
W/L=600/0.2
I =1 mA
1/2
Noise Voltage Spectrum [nV/Hz ]
100
 =0.84
D
f
|V |=600 mV
DS
10
 =1.12
f
1
NMOS
PMOS
3
10
10
4
10
5
10
6
10
7
Frequency [Hz]
Slope f of the 1/f noise term is significantly smaller than 1 in NMOS transistors
and larger than 1 in PMOS devices
VI International Meeting on Front-End Electronics, Perugia, May 18th 2006
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Slope coefficient f
1.6
1.6
90 nm tech
130 nm tech
1.4
1.4
PMOS
1.2
PMOS


f
f
1.2
1
1
0.8
0.8
NMOS
NMOS
0.6
0.6
0
0.2
0.4
0.6
0.8
Drain Current [mA]
1
1.2
0
0.2
0.4
0.6
0.8
1
Drain Current [mA]
In the examined operating region, f does not exhibit any clear dependence on the
drain current or on the channel length
f between 1 and 1.3 for PMOS devices, between 0.8 and 1 for NMOS devices
VI International Meeting on Front-End Electronics, Perugia, May 18th 2006
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1.2
Slope coefficient f
1.6
PMOS
NMOS
STM
130 nm
1.4
TSMC
250 nm

f
1.2
1
0.8
STM
90 nm
0.6
0.05
0.1
STM
180 nm
0.15
0.2
STM
350 nm
0.25
0.3
0.35
0.4
Minimum Feature Size [mm]
Very similar behavior of f was detected through different CMOS generations and
different foundries
VI International Meeting on Front-End Electronics, Perugia, May 18th 2006
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1/f noise coefficient kf vs gate length
40
40
-25
20
15
10
NMOS
W=1000 mm
5
Id=0.10
Id=0.25
Id=0.50
Id=0.75
Id=1.00
30
Hz
25
STM 90 nm
35
Kf [J 10
Kf [J 10
-25
Hz
(alpha-1)
]
30
mA
mA
mA
mA
mA
]
Id=0.10
Id=0.25
Id=0.50
Id=0.75
Id=1.00
(alpha-1)
STM 130 nm
35
mA
mA
mA
mA
mA
25
NMOS
W=600 mm
20
15
10
5
0
0
0
0.2
0.4
0.6
0.8
Channel Length [mm]
1
1.2
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
Channel Length [mm]
In the case of the 130 nm technology, short channel devices (L<0.5 mm) exhibit a
flicker noise coefficient larger than for NMOSFETs with longer channels
The same behavior concerns devices with L<0.2 mm in the case of the 90 nm
technology
VI International Meeting on Front-End Electronics, Perugia, May 18th 2006
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0.8
1/f noise coefficient kf vs Vov
120
120
STM 130 nm
PMOS
100
k [J 10
40
f
NMOS
60
90 nm
40
f
k [J 10
-25
60
130 nm
80
Hz
Hz
-25
]
PMOS
80
(alpha-1)
(alpha-1)
]
100
20
20
0
-0.05
0
0.05
0.1
Gate Overdrive Voltage [V]
0.15
0.2
0
-0.05
0
0.05
0.1
0.15
Gate Overdrive Voltage [V]
In PMOS devices, flicker noise coefficient is clearly bias dependent (dependence is
weaker in STM 90 nm technology)
In NMOS transistors kf is to a large extent independent of the overdrive voltage VOV
VI International Meeting on Front-End Electronics, Perugia, May 18th 2006
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0.2
60Co
-rays effects on device performances
ID increase in the
subthreshold region of
NMOS: edge effects due
to radiation-induced
charge at the shallow
trench isolation (STI)
oxide.
The effect is larger in
devices with a shorter
channel, affecting ID
regions of interest for
low-power applications
W/L = 1000/0.5
10-2
10-4
ID [A]
PMOS
10-6
NMOS
before irradiation
10 MRad
10-8
10-10
-1.2
-0.8
-0.4
0
0.4
0.8
1.2
(ID = 100 mA).
VGS [V]
0.13 µm technology (open-structure layout)
VI International Meeting on Front-End Electronics, Perugia, May 18th 2006
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60Co
-rays effects on device performances
100
1/2
Noise Voltage Spectrum [nV/Hz ]
1/2
Noise Voltage Spectrum [nV/Hz ]
100
NMOS
I = 100 mA
D
W/L = 1000/0.35
10
1
before irradiation
10 Mrad
0.1 3
10
10
4
10
5
f [Hz]
10
6
10
7
10
8
NMOS
I = 1 mA
D
W/L = 1000/0.35
10
1
before irradiation
10 Mrad
0.1 3
10
10
4
10
5
10
6
10
7
f [Hz]
In short-channel NMOS, at low ID (around 100 mA) 1/f noise increases by a
much larger extent than at higher drain currents.
This may be correlated with the ID increase in the subthreshold region,
meaning that the shallow trench oxide contributes in determining the 1/f noise
properties of irradiated open-structure devices.
VI International Meeting on Front-End Electronics, Perugia, May 18th 2006
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10
8
Conclusions
Static, signal and noise measurements have been performed on devices
belonging to two different CMOS technology nodes, namely the 130 nm and
90 nm STM processes
Channel thermal noise equations developed to describe the device behavior in
the considered operating regions provide a reliable model, with short channel
effect playing a minor role in both the considered processes
1/f noise results confirm the behavior detected in previous submicron processes
as far as the dependence on device polarity and bias and gate geometry is
concerned
Extracted noise parameters show that using the 90 nm process may ensure an
improvement in the noise performances in applications where large signal
dynamic range is not needed while miniaturization can be an asset
Characterization of the 90 nm technology will be completed with radiation
hardness tests (open structure vs enclosed layout, study of possible STI effects)
VI International Meeting on Front-End Electronics, Perugia, May 18th 2006
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Backup slides
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Channel thermal noise coefficient

1 1 2 
 u,

1 u  2 3 
u
IDL
I*z W
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Low noise charge preamplifier design
Circuit designers can take advantage of single device characterization to predict
noise behavior of charge sensitive amplifiers
Equivalent noise charge is the figure of merit to be minimized:
ENC  CD  Cg  A1
4k B T 1
kf
1

 2  f A 2  f 
1 f
gm t p
COX WL t p
Channel thermal
noise contribution
Flicker noise
contribution
• CD detector capacitance
• CG preamplifier input
capacitance
• tp peaking time
• A1 A2 shaping coefficients
Data extracted from single transistor characterization can be used to plot
minimum ENC as a function of the main design parameters (peaking time, power
dissipation, polarity and dimensions of the preamplifier input device)
It is interesting to assess whether (and if so to what extent) using a more scaled
technology may improve noise performances
VI International Meeting on Front-End Electronics, Perugia, May 18th 2006
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ENC vs peaking time
C =20 pF
P
=0.25 mW
D.max
L=0.20 mm
ENC was evaluated in the
case of a second order,
unipolar (RC2-CR) shaping
processor
-
Optimum ENC [e rms]
D
1000
NMOS
STM 130 nm
PMOS
STM 90 nm
100
10
10
2
10
3
Peaking time [ns]
In the explored peaking time and power range, PMOS input device always provides better
noise performances than NMOS input (except for the 130 nm process at tp close to 10 ns)
Using the 90 nm process may yield quite significant improvement with respect to the
130 nm technology, especially when NMOS input charge preamplifiers are considered
VI International Meeting on Front-End Electronics, Perugia, May 18th 2006
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ENC vs dissipated power
5000
3000
Optimum ENC [e rms]
STM 90 nm
STM 130 nm
STM 90 nm
3000
STM 130 nm
-
-
Optimum ENC [e rms]
5000
NMOS
C =20 pF
1000
D
800
L=0.20 mm
t =20 ns
600
PMOS
C =20 pF
1000
D
800
L=0.20 mm
t =20 ns
600
p
400
p
400
0.01
0.1
Dissipated power [mW]
1
0.01
0.1
1
Dissipated power [mW]
At tp=20 ns, noise performances provided by NMOS and PMOS input devices in the 90 nm
technology are comparable
Better noise-power trade-off can be achieved by using the 90 nm technology
VI International Meeting on Front-End Electronics, Perugia, May 18th 2006
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Transconductance in all inversion
regions
gm 
ID
2
,
nVT 1 4u  1
u
IDL
I*z W
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