Survey
* Your assessment is very important for improving the workof artificial intelligence, which forms the content of this project
* Your assessment is very important for improving the workof artificial intelligence, which forms the content of this project
MAC Processor for BASUMA Wireless Body Area Network Z. Stamenković, D. Dietterle, G. Panić, W. Bocer, G. Schoof, and J.-P. Ebert IHP Im Technologiepark 25 15236 Frankfurt (Oder) Germany IHP Im Technologiepark 25 15236 Frankfurt (Oder) Germany www.ihp-microelectronics.com © 2007 - All rights reserved Motivation • Up to date no stable operating BAN available Enable exchange between sensors for intelligent reasoning about patients state • Data rates > 1 Mbps at low power are challenging Essential for small battery-powered devices Hurry-up-and-sleep approach • Smart wireless medical sensors Enable continuous health monitoring • Single chip solution (SOC) Lowers power consumption, weight, and allows different packaging IHP Innovations for High Performance Microelectronics Slide 2 © 2007 - All rights reserved Body Area System for Medical Applications … … Heart Hearttransplantation transplantation Breast Breastcancer cancer l Apps COPD COPD ECG Sensor SW SpO2 Sensor Lung ROS Sound Sensor Monitor Mobile Phone … Middleware Application Framework BASUMA Application Framework Wireless Communication Protocols IEEE 802.15.3 Embedded Operating System Reflex OS HW Processor IHP Innovations for High Performance Microelectronics LEON2 Radio Ultra Wideband (UWB) Slide 3 © 2007 - All rights reserved BASUMA • Body Area System for Ubiquitous Multimedia Applications Generic wireless communication platform Long-term health monitoring of chronically ill patients IHP Innovations for High Performance Microelectronics Slide 4 © 2007 - All rights reserved BASUMA Communication Module IHP Innovations for High Performance Microelectronics Slide 5 © 2007 - All rights reserved IEEE 802.15.3 MAC Protocol • IEEE 802.15.3 standard provides Ad-hoc networking Quality of service and security Various power management modes Physical layer data rates from 11 to 55 Mbit/s • Medium Access Control (MAC) protocol functionality Data path Cyclic redundancy check (CRC) sum calculation Encryption and decryption of the frame payload Interfacing with the physical layer and frame buffering Control path • Profiling of the software using LEON-2 instruction set simulator Time-critical protocol functions are iteratively removed from the software model and put into a hardware component IHP Innovations for High Performance Microelectronics Slide 6 © 2007 - All rights reserved MAC Protocol Model Higher protocol layers Data path Control path RequestHandling PNC-specific functions Association Scan PiconetOperation PNC-specific functions Sync. TransportEngine TxControl RxControl Digital baseband processing IHP Innovations for High Performance Microelectronics Slide 7 © 2007 - All rights reserved Protocol Functions Designed in Hardware • In receive direction, to retrieve frame data from the physical layer byte by byte, perform filtering and CRC check, and to store the data by means of direct memory access • In transmit direction, to retrieve frame data from a memory location, calculate and append the check sum, and to push the data to the physical layer • To signal a successful reception or transmission of a frame to the processor by an interrupt • To analyze received and transmitted beacon frames and extract information on channel time allocations • To manage a queue of frames and to select an appropriate frame for transmission • At the start of a time slot or following a frame transmission, to query a new frame from the queue and, in the case that the frame must be acknowledged, wait for the acknowledgment frame • To perform the backoff procedure in the contention access period • To send an acknowledgment at the right time upon reception of a frame that needs to be acknowledged • To calculate the actual duration of a frame transmission based on its payload length and data rate IHP Innovations for High Performance Microelectronics Slide 8 © 2007 - All rights reserved Architecture of MAC Protocol Accelerator IHP Innovations for High Performance Microelectronics Slide 9 © 2007 - All rights reserved Flash Interface IHP Innovations for High Performance Microelectronics Slide 10 © 2007 - All rights reserved System Architecture BIST UART 0 DSU+ UART AHB 8 Reg. Windows 4 kByte 8 D- Cache Memory CTL AHB CTL 64 kByte FLASH BIST SRAM IHP Innovations for High Performance Microelectronics UART 1 APB IRQ CTL GPIO 16 16xxGPIO LEON-2 Core BASUMA MAC Bridge Bridge 4 kByte 8 I- Cache 2x Timer Scan Test FLASH Slide 11 © 2007 - All rights reserved Design Flow Applications System System Specification Specification Library Database Library Database New Modules Configurable Modules New Modules CustomisableRTL Modules (synthesisable code) (synthesisable RTL code) Predefined Predefined Modules Modules (RTL, standard cells, (synthesised net-list, SDF synthesised net-lists, and/or LEF) layouts) HDL TopModel Module Definition HDL Definition no no Logic Re-synthesis Sufficient? Simulation Simulation OK? OK? yes yes Logic Logic Synthesis Synthesis no no Layout Re-synthesis Sufficient? Simulation Simulation OK? OK? Test TestBenches Benches yes yes Layout LayoutGeneration Synthesis no Simulation Simulation OK? OK? yes Final Chip Layout IHP Innovations for High Performance Microelectronics Slide 12 © 2007 - All rights reserved Implementation • Installation of the LEON-2 release • Adaptation of the configuration tool (to include IHP’s library) • VHDL coding of MAC protocol accelerator and flash interface • Implementation of data and instruction caches including BIST • Logic synthesis of the design • Implementation of scan chain • Generation and verification of the chip layout • Simulation (functional, post-synthesis and post-layout net-list) • Scan test vectors generation (ATPG) • BIST and scan test simulation • Adaptation of testbenches (SPARC CC installed) • EVCD test vectors generation (with and without timing data) • Test specification IHP Innovations for High Performance Microelectronics Slide 13 © 2007 - All rights reserved Chip Features Area (mm2) 31.9 Signal Ports 126 Power Ports 24 BIST Ports 12 Scan Ports 1(3) Transistors (x106) 3.1 Scanable Flip-Flops (x103) 15 Cache Memories (kbytes) 9.5 Flash Memory (kbytes) 64 Power/Frequency (mW/MHz) 15 Maximum Frequency limited by Flash (MHz) 25 IHP Innovations for High Performance Microelectronics Slide 14 © 2007 - All rights reserved Summary • Hardware/software co-design and implementation of the processor configured to support IEEE 802.15.3 MAC protocol of the Body Area System for Ubiquitous Multimedia Applications (BASUMA) • Implemented SOC is a good candidate for the MAC processor of the BASUMA communication module in respect of performance, speed, and power • Next phase in development of the wireless body area network technology at IHP TANDEM project IHP Innovations for High Performance Microelectronics Slide 15 © 2007 - All rights reserved