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Introduction to
CMOS VLSI
Design
Introduction
Manoel E. de Lima
David Harris - Harvey Mudd College
Introduction
 Integrated circuits: many transistors on one chip.
 Very Large Scale Integration (VLSI): very many
 Complementary Metal Oxide Semiconductor
– Fast, cheap, low power transistors
 Today: How to build your own simple CMOS chip
– CMOS transistors
– Building logic gates from transistors
– Transistor layout and fabrication
 Rest of the course: How to build a good CMOS chip
0: Introduction
CMOS VLSI Design
Slide 2
WHY VLSI DESIGN?
Money, technology, civilization
CMOS VLSI Design
Annual Sales
 1018 transistors manufactured in 2003

100 million for every human on the planet
Global Semiconductor Billings
(Billions of US$)
200
150
100
50
0
1982
1984
1986
1988
1990
1992
1994
Year
CMOS VLSI Design
1996
1998
2000
2002
Digression: Silicon Semiconductors



Modern electronic chips are built mostly on silicon substrates
Silicon is a Group IV semiconducting material
crystal lattice: covalent bonds hold each atom to four neighbors
Si
Si
Si
Si
Si
Si
Si
Si
Si
http://onlineheavytheory.net/silicon.html
CMOS VLSI Design
Silicon Lattice
 Transistors are built on a silicon substrate
 Silicon is a Group IV material
 Forms crystal lattice with bonds to four neighbors
0: Introduction
Si
Si
Si
Si
Si
Si
Si
Si
Si
CMOS VLSI Design
Slide 6
Dopants





Silicon is a semiconductor
Pure silicon has no free carriers and conducts poorly
Adding dopants increases the conductivity
Group V: extra electron (n-type)
Group III: missing electron, called hole (p-type)
0: Introduction
Si
Si
Si
Si
Si
Si
As
Si
Si
B
Si
Si
Si
Si
Si
-
+
+
-
CMOS VLSI Design
Si
Si
Si
Slide 7
p-n Junctions
 A junction between p-type and n-type semiconductor
forms a diode.
 Current flows only in one direction
0: Introduction
p-type
n-type
anode
cathode
CMOS VLSI Design
Slide 8
A Brief History
Invention of the Transistor
 Vacuum tubes ruled in first half of 20th century Large,
expensive, power-hungry, unreliable
 1947: first point contact transistor (3 terminal devices)

Shockley, Bardeen and Brattain at Bell Labs
CMOS VLSI Design
A Brief History, contd..
 1958: First integrated circuit



Flip-flop using two transistors
Built by Jack Kilby (Nobel Laureate) at Texas Instruments
Robert Noyce (Fairchild) is also considered as a co-inventor
Kilby’s IC
smithsonianchips.si.edu/ augarten/
CMOS VLSI Design
A Brief History, contd.
 First Planer IC built in 1961
 2003
 Intel Pentium 4 processor (55 million transistors)
 512 Mbit DRAM (> 0.5 billion transistors)
 53% compound annual growth rate over 45 years
 No other technology has grown so fast so long
 Driven by miniaturization of transistors
 Smaller is cheaper, faster, lower in power!
 Revolutionary effects on society
CMOS VLSI Design
MOS Integrated Circuits
 1970’s processes usually had only nMOS transistors
Inexpensive, but consume power while idle
 1980s-present: CMOS processes for low idle power
Intel 1101 256-bit SRAM
Intel 4004 4-bit
CMOS VLSI Design
Proc
Moore’s Law
 1965: Gordon Moore plotted transistor on each chip


Fit straight line on semilog scale
Transistor counts have doubled every 26 months
1,000,000,000
Integration Levels
100,000,000
10,000,000
Transistors
Intel486
1,000,000
80286
100,000
Pentium 4
Pentium III
Pentium II
Pentium Pro
Pentium
Intel386
SSI:
10 gates
MSI: 1000 gates
8086
10,000
8080
LSI:
8008
4004
1,000
1970
1975
1980
1985
1990
1995
2000
Year
http://www.intel.com/technology/silicon/mooreslaw/
CMOS VLSI Design
10,000 gates
VLSI: > 10k gates
Transistor Types
 Bipolar transistors
npn or pnp silicon structure
 Small current into very thin base layer controls large
currents between emitter and collector
 Base currents limit integration density
 Metal Oxide Semiconductor Field Effect Transistors
 nMOS and pMOS MOSFETS
 Voltage applied to insulated gate controls current
between source and drain
 Low power allows very high integration
 First patent in the ’20s in USA and Germany
 Not widely used until the ’60s or ’70s

CMOS VLSI Design
nMOS Transistor
 Four terminals: gate, source, drain, body
 Gate – oxide – body stack looks like a capacitor
– Gate and body are conductors
– SiO2 (oxide) is a very good insulator
– Called metal – oxide – semiconductor (MOS)
capacitor
Source
Gate
Drain
Polysilicon
– Even though gate is
SiO2
no longer made of metal
n+
n+
p
0: Introduction
CMOS VLSI Design
bulk Si
Slide 15
nMOS Operation
 Body is commonly tied to ground (0 V)
 When the gate is at a low voltage:
– P-type body is at low voltage
– Source-body and drain-body diodes are OFF
– No current flows, transistor is OFF
Source
Gate
Drain
Polysilicon
SiO2
0
n+
n+
S
p
0: Introduction
D
bulk Si
CMOS VLSI Design
Slide 16
nMOS Operation Cont.
 When the gate is at a high voltage:
– Positive charge on gate of MOS capacitor
– Negative charge attracted to body
– Inverts a channel under gate to n-type
– Now current can flow through n-type silicon from
source through channel to drain, transistor is ON
Source
Gate
Drain
Polysilicon
SiO2
1
n+
n+
S
p
0: Introduction
D
bulk Si
CMOS VLSI Design
Slide 17
pMOS Transistor
 Similar, but doping and voltages reversed
– Body tied to high voltage (VDD)
– Gate low: transistor ON
– Gate high: transistor OFF
– Bubble indicates inverted behavior
Source
Gate
Drain
Polysilicon
SiO2
p+
p+
n
0: Introduction
CMOS VLSI Design
bulk Si
Slide 18
Power Supply Voltage
 GND = 0 V
 In 1980’s, VDD = 5V
 VDD has decreased in modern processes
– High VDD would damage modern tiny transistors
– Lower VDD saves power
 VDD = 3.3, 2.5, 1.8, 1.5, 1.2, 1.0, …
0: Introduction
CMOS VLSI Design
Slide 19
Transistors as Switches
 We can view MOS transistors as electrically
controlled switches
 Voltage at gate controls path from source to drain
d
nMOS
pMOS
g=1
d
d
OFF
g
ON
s
s
s
d
d
d
g
OFF
ON
s
0: Introduction
g=0
s
CMOS VLSI Design
s
Slide 20
Transistors
Level
Symbol
Switch Conditions
Strong 1
1
P-switch gate=0, source=Vdd
Weak
1
1
N-switch gate=1, source=Vdd
Strong 0
0
N-switch gate=1, source=Vss
Weak
0
P-switch gate=0, source=Vss
Z
N-switch gate=0, or P-switch gate=1
0
High impedance
Input
0
Output
Good 0
Input
0
Output
poor 0
Input
1
Output
poor 1
Input
1
Output
good 1
0: Introduction
CMOS VLSI Design
Slide 21
Input
0
Output
Good 0
Input
0
Output
poor 0
Input
1
Output
poor 1
Input
1
Output
good 1
0: Introduction
CMOS VLSI Design
Slide 22
CMOS Inverter
A
VDD
Y
0
1
A
A
Y
Y
GND
0: Introduction
CMOS VLSI Design
Slide 23
CMOS Inverter
A
VDD
Y
0
1
OFF
0
A=1
Y=0
ON
A
Y
GND
0: Introduction
CMOS VLSI Design
Slide 24
CMOS Inverter
A
Y
0
1
1
0
VDD
ON
A=0
Y=1
OFF
A
Y
GND
0: Introduction
CMOS VLSI Design
Slide 25
CMOS Inverter
Vdd
1- Vin = Vdd
Q1
Análise do circuito:
Vdd=+5V
Ids
Roff
Ron Vout
0V
Vin
Q2
Vout
Vss
Cálculo de Vout
Vdd = Ids(Roff+Ron)
Vdd = Ids.Roff+Ids.Ron
Vdd = Ids.Roff+Vout
Vout = Vdd-Ids.Roff 
Id
Cload
=>
=>
=>
0V
Ron < 1 Kohms
Roff  1010Kohms
Ids é pequeno, mas Roff é bastante grande
CMOS VLSI Design
CMOS Inverter
• Note que Vh = 5V, VL = 0V, e que Ids = 0A.
• Isto significa que não existe praticamente dissipação de potência.
CMOS VLSI Design
CMOS Inverter
Ron  1 K
Transistor não conduz
+5V
+5V
R
In
Vih=´1´
Vol(max)
Ron  1 K
Out
Iil
Iol
Vil(max)
GND
Transistor conduz
GND
Capacitor carregado (´1´)
Tensão(V)
Nível ´0´
Vil(max)
Tempo (seg)
CMOS VLSI Design
CMOS Inverter
Vdd
2- Vin = 0V
Q1
Análise do circuito:
Vin
Vdd=+5V
Ids
Ron
Roff Vout
0V
Q2
Vout
Vss
Cálculo de Vout
Vdd = Ids(Roff+Ron)
Vdd = Ids.Roff+Ids.Ron
Vdd = Vout+Ids.Ron
Vout = Vdd-Ids.Ron 
Ron < 1 Kohms
Roff  1010Kohms
Ids é muito pequeno
CMOS VLSI Design
Id
=>
=>
=>
Vdd=5V
Cload
CMOS Inverter
• Note que Vh = 5V, VL = 0V, e que Ids = 0A.
• Isto significa que não existe praticamente dissipação de potência.
CMOS VLSI Design
CMOS Inverter
Ron  1 K
+5V
Transistor conduz
R
In
Vil=0
Roff  1010
+5V
X
Out
Iih
Ioh
Voh(min)
Vih(min)
GND
GND
Transistor não conduz
Capacitor
Tensão(V)
Vih(min)
Nível ´1´
Tempo (seg)
CMOS VLSI Design
CMOS NAND Gate
A
B
0
0
0
1
1
0
1
1
Y
Y
A
B
0: Introduction
CMOS VLSI Design
Slide 32
CMOS NAND Gate
A
B
Y
0
0
1
0
1
1
0
1
1
0: Introduction
ON
ON
Y=1
A=0
B=0
CMOS VLSI Design
OFF
OFF
Slide 33
CMOS NAND Gate
A
B
Y
0
0
1
0
1
1
1
0
1
1
0: Introduction
OFF
ON
Y=1
A=0
B=1
CMOS VLSI Design
OFF
ON
Slide 34
CMOS NAND Gate
A
B
Y
0
0
1
0
1
1
1
0
1
1
1
0: Introduction
ON
A=1
B=0
CMOS VLSI Design
OFF
Y=1
ON
OFF
Slide 35
CMOS NAND Gate
A
B
Y
0
0
1
0
1
1
1
0
1
1
1
0
0: Introduction
OFF
A=1
B=1
CMOS VLSI Design
OFF
Y=0
ON
ON
Slide 36
Lógica Combinacional
saída
 Porta NAND
0
A
0
1
1
1
B
Vcc (‘1’)
1
1
Porta NAND de
n-entradas
Vcc
0
(A+B)
P
Vcc
P
B
A
C
saída
Saída
Dual Lógico
N
(A B)
A
Saída
A
B
A
C
B
N
B
GND
GND (‘0’)
n
GND
CMOS VLSI Design
n
CMOS NOR Gate
A
B
Y
0
0
1
0
1
0
1
0
0
1
1
0
0: Introduction
A
B
Y
CMOS VLSI Design
Slide 38
Lógica Combinacional
saída
 Porta NOR
Vcc (‘1’)
A
0
0
1
1
0
1
0
0
B
P
n
Vcc
(A B)
A
P
A
B
Dual Lógico
saída
saída
N
N
A
Vcc
B
Saída
C
B
(A+B)
GND
A
B
n
C
GND
GND (‘0’)
CMOS VLSI Design
3-input NAND Gate
 Y pulls low if ALL inputs are 1
 Y pulls high if ANY input is 0
Y
A
B
C
0: Introduction
CMOS VLSI Design
Slide 40
Summary
 MOS Transistors are stack of gate, oxide, silicon
 Can be viewed as electrically controlled switches
 Build logic gates out of switches
0: Introduction
CMOS VLSI Design
Slide 41