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JOP Java Optimized Processor DI Martin Schöberl Content Targets Java Virtal Machine Three different architectures Datapath of JOP3 First results Targets Small processor Fits in a main stram FPGA Efficient execution of byte codes JVM real time enabled organization of local memory ? Multi processor on a single chip ? Java Virtual Machine 32 (64) Bit stack machine Variable length instructions Simple to very complex instructions Symbolic references Stack, heap, constants and code First Approach Accu/Register Machine RISC like instruction set 16 Bit instruction set 32 Bit datapath 3 stage pipeline All instructions single cycle Larg register file (up to 1024) JVM complete in SW Second Approach + special register SP, AR 16 register + 16 constants Stack in local memory 8 Bit instruction Memory interface ‚extern‘ Byte code fetch/decode in HW 2+3 stage pipeline JVM instruction min. 3 cycles JOP3 Stack machine Byte code is instruction set 8 Bit microcode Basic JVM instructions single cycle 4 stage pipeline No traps for complex instructions JOP3 Fetch + P C 1 RAM jbc J I N S ROM + O P D H I R microcode + J B R A -3 1 + J P C JOP3 Read/Write A SP + vp 1 + vp 2 + vp 3 1 SP M + -1 2 SP P + 1 A 3 I R R D A D D R SPM J I N S + vp ix + cp ix vp A cp A W R A D D R JOP3 Execute - + RAM B wrena ld and or xor rdaddr shr wraddr dout A din sp vp0 cp imm I O R Status Cores run on Altera ACEX 1K30-3 Periphery: IO port, SRAM- and Flash interface, UART, ECP First real application under development Performance ‚useless‘ benchmark (prime) 486SX25: 1.2M transistors e.g. 300k gates ACEX 1K30: 24 MHz, 30k gates 486SX25 JVM -nojit 486SX25 JIT JOP1 8 Bit ext. mem. JOP2 local mem. JOP3 local mem. 19.6 s 5.0 s 79 s 3.4 s 1.7 s 1.00 3.91 0.25 5.77 11.3 http://www.jopdesign.com/ Documentation as HTML All VHDL, ASM and Java sources Actual version for download