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TCAD Simulation for
SOI Pixel Detector
October 31, 2007
IEEE-NSS, Honolulu, Hawaii, USA
Hirokazu Hayashi, Hirotaka Komatsubara (Oki Elec.
Ind. Co.),
Yasuo Arai, Masashi Hazumi (KEK),
Yuji Saegusa (TIT)
for the SOIPIX group
SOIPIX collaborators
KEK Detector Technology Project : [SOIPIX Group]
Y. Arai*, M. Hazumi, Y. Ikegami, T. Kohriki, O. Tajima, S.
Terada, T. Tsuboyama, Y. Unno, H. Ushiroda,
H. IkedaA,
K. HaraB, H. MiyakeB,
H. IshinoC, Y. SaegusaC,
T. KawasakiD, E. MartinE, G. VarnerE, H. TajimaF, K. FukudaG,
H. HayashiG, H. KomatsubaraG, J. IdaG , M. OhnoG
KEK、JAXAA, U. TsukubaB, TITC,
Niigata U.D, U. HawaiiE, SLACF,
OKI Elec. Ind. Co.G
(*)—contact person
2006/10/31
M. Hazumi (KEK)
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Overview
TCAD = Technology CAD
• ENEXSS (Environment for NExt Simulation System)
• Developed by Selete (Semiconductor Leading Edge Technologies)
( http://www.selete.co.jp/?lang=EN )
• Full 3D process/device simulation !
• Commercially available from TCAD-International
( http://www.tcad-international.com/ENEXSS_e.html )
Real
Specifications
Function design
LSI Manufacturing
Fast 
Deeper
understanding 
Virtual
TCAD
Logic design
Circuit design
Process data
Device data
Process
simulation
Layout design
~3mon. 
Mask fabrication
Device
production
2006/10/31
Characterization
Prototyping
Device
simulation
•
•
•
•
•
Topics covered in this talk
Back gate effect
Circuit-sensor crosstalk
Implantation parameters
Guard ring design
Pixel layout
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Back gate effect
Substrate voltage acts as Back Gate,
and changes transistor threshold.
TCAD
0.5
0.4
0.3
0.2
0.1
0
-0.1
-0.2
-0.3
-0.4
ENEXSS TCAD
2006/10/31
M. Hazumi (KEK)
20
-10
0
+10
Back bias (V)
VB (V)
16
12
8
4
0
-4
-8
-12
-20
-16
V
-20
Measurement
Threshold voltage (V)
Back Gate
+20
4
Back gate effect:
mitigation with p+ implants
distance (D) (40 – 2 mm)
NMOS
BOX (200nm)
(5 mm wide P+, 1 x 1020 cm-3)
 Bulk: N- (~700ohm cm, 6 x 10
12
cm-3) 350mm

p+ implant (0V) for I/O buffer
Threshold voltage
D
Vth (V)
0.5
0.4
2m
0.3
5m
0.2
6m
Measurement
(10MHz clock)
Out
10m
0
50
100
20m
30m
40m
-0.2
-0.3
2006/10/31
Back bias
= 40V
7m
0.1
-0.1 0
MPW06
V_B (V)
Back bias
M. Hazumi (KEK)
In
Much improved !
5
Circuit-sensor crosstalk
Signals in the circuitry very close to the sensor
may inject noise to the sensor.
Input
OK for charge-integrated device.
Need some care for other cases
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Implantation parameters
Find the best ion and beam energy to achieve the
highest breakdown voltage (vital important for full depletion)
Example 1)
Ion #2
Ion #1
2mm
Vbreak (V) = +88.5V
Vbreak
Breakdown voltage (v)
Example 2)
160
140
120
100
80
60
40
20
0
= +102.4V
• “Deeper” implantation mitigates
impact ionization (II) and results
in
a higher
breakdown voltage.
Vbreak
(V)
• ~20% improvement expected by
doing both.
0
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50
100
150
200
N+ implantation energy (KeV)
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Test structure (strip sensor)
MPW06
Standard
New
Measurement
~20% improvement observed
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Guard ring design
Better guard ring design also helpful to improve breakdown
voltage.
SOI pixel detector
...
...
Pixels
MPW06
1 guard + 1bias
VSS Ring
I/O
MPW06
2 guards + 1bias
Bias Ring
Guard Ring
20V at the back side
100000
Bias Ring edge
E [V/cm]
80000
1 guard ring (MPW06)
2 guard rings (next
submission)
60000
40000
20000
Bias
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0
10
Guard
Guard
20
An additional guard ring
is effective to reduce
the electric field
concentration.
30
40
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d [um]
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Pixel layout
A
For digital readout, charge sharing
curve at the cell boundary should
be as steep as possible.
cell A
B
cell B
Note that in our design there are
4 p+ implants in one cell connected
in the readout.
MIP-like charge injection with TCAD
for the 3 layouts shown below
x
①
0
5
4
②
③
3
2
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10
20
15
+:①
+:②
+:③
[mm]
Narrower gap b/w
two cells (③)
slightly better.
16
17
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x
Summary
• Back gate effect largely mitigated with additional p+ implants
near the circuitry.
• Circuit-sensor crosstalk is not an issue for digital pixel readout
with charge integration.
• Higher breakdown voltage with improved implantation
parameters (~20% achieved)
• Additional guard ring can reduce the electric field by factor ~2.
• Implantation gap b/w two cells should be minimized (present
design seems close to the best)
• Good prospects for thinned fully-depleted SOI pixel !
2006/10/31
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