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Introduction to
CMOS VLSI
Design
Lecture 1:
Circuits & Layout
Manoel E. de Lima – CIn – UFPE
David Harris
Harvey Mudd College
Spring 2004
Outline





CMOS Gate Design
Pass Transistors
CMOS Latches & Flip-Flops
Standard Cell Layouts
Stick Diagrams
1: Circuits & Layout
CMOS VLSI Design
Slide 2
CMOS Gate Design
 Activity:
– Sketch a 4-input CMOS NAND gate
1: Circuits & Layout
CMOS VLSI Design
Slide 3
CMOS Gate Design
 Activity:
– Sketch a 4-input CMOS NOR gate
A
B
C
D
Y
1: Circuits & Layout
CMOS VLSI Design
Slide 4
Complementary CMOS
 Complementary CMOS logic gates
– nMOS pull-down network
– pMOS pull-up network
pMOS
pull-up
network
inputs
output
Pull-up OFF
Pull-up ON
Pull-down OFF Z (float)
1
Pull-down ON
X (crowbar)
1: Circuits & Layout
0
CMOS VLSI Design
nMOS
pull-down
network
Slide 5
Series and Parallel




nMOS: 1 = ON
pMOS: 0 = ON
Series: both must be ON
Parallel: either can be ON
a
a
0
g1
g2
(a)
(b)
a
g1
g2
(c)
a
g1
g2
b
1: Circuits & Layout
CMOS VLSI Design
0
1
b
b
OFF
OFF
OFF
ON
a
a
a
a
0
1
1
1
0
1
b
b
b
b
ON
OFF
OFF
OFF
a
a
a
a
0
0
b
1
b
0
b
1
1
0
g2
a
b
a
g1
a
0
0
b
(d)
a
0
1
1
0
1
1
b
b
b
b
OFF
ON
ON
ON
a
a
a
a
0
0
0
1
1
0
1
1
b
b
b
b
ON
ON
ON
OFF
Slide 6
Conduction Complement
 Complementary CMOS gates always produce 0 or 1
 Ex: NAND gate
– Series nMOS: Y=0 when both inputs are 1
– Thus Y=1 when either input is 0
Y
– Requires parallel pMOS
A
B
 Rule of Conduction Complements
– Pull-up network is complement of pull-down
– Parallel -> series, series -> parallel
1: Circuits & Layout
CMOS VLSI Design
Slide 7
Compound Gates
 Compound gates can do any inverting function
nMOS
 Ex: A.B+C.D
AB
00
01
11
10
00
1
1
0
1
01
1
1
0
1
11
0
0
0
0
10
1
1
0
1
CD
pMOS
nMOS+pMOS
1: Circuits & Layout
CMOS VLSI Design
Slide 8
Example: O3AI
 Y = (A+B+C).D
Vcc
1: Circuits & Layout
CMOS VLSI Design
Slide 9
Signal Strength
 Strength of signal
– How close it approximates ideal voltage source
 VDD and GND rails are strongest 1 and 0
 nMOS pass strong 0
– But degraded or weak 1
 pMOS pass strong 1
– But degraded or weak 0
 Thus nMOS are best for pull-down network
1: Circuits & Layout
CMOS VLSI Design
Slide 10
Pass Transistors
 Transistors can be used as switches
g
s
d
g
s
d
1: Circuits & Layout
CMOS VLSI Design
Slide 11
Pass Transistors
 Transistors can be used as switches
g=0
g
s
d
s
d
Input g = 1 Output
0
strong 0
g=1
s
d
g=0
g
s
s
g=1
Input
d
d
g=1
s
1: Circuits & Layout
1
d
CMOS VLSI Design
degraded 1
g=0
0
Output
degraded 0
g=0
strong 1
Slide 12
Transmission Gates
 Pass transistors produce degraded outputs
 Transmission gates pass both 0 and 1 well
1: Circuits & Layout
CMOS VLSI Design
Slide 13
Transmission Gates
 Pass transistors produce degraded outputs
 Transmission gates pass both 0 and 1 well
Input
g
a
b
gb
a
g = 0, gb = 1
a
b
g = 1, gb = 0
0
strong 0
g = 1, gb = 0
a
b
g = 1, gb = 0
strong 1
1
g
g
b
gb
1: Circuits & Layout
a
g
b
gb
Output
a
b
gb
CMOS VLSI Design
Slide 14
Tristates
 Tristate buffer produces Z when not enabled
EN
A
0
0
0
1
1
0
1
1
EN
Y
Y
A
EN
Y
A
EN
1: Circuits & Layout
CMOS VLSI Design
Slide 15
Tristates
 Tristate buffer produces Z when not enabled
EN
A
Y
0
0
Z
0
1
Z
1
0
0
1
1
1
EN
Y
A
EN
Y
A
EN
1: Circuits & Layout
CMOS VLSI Design
Slide 16
Nonrestoring Tristate
 Transmission gate acts as tristate buffer
– Only two transistors\
• Noise on A is passed on to Y
EN
A
Y
EN
1: Circuits & Layout
CMOS VLSI Design
Slide 17
Tristate Inverter
 Tristate inverter produces restored output
– Violates conduction complement rule
– Because we want a Z output
A
EN
Y
EN
1: Circuits & Layout
CMOS VLSI Design
Slide 18
Tristate Inverter
 Tristate inverter produces restored output
– Violates conduction complement rule
– Because we want a Z output
A
A
A
EN
Y
Y
Y
EN = 0
Y = 'Z'
EN = 1
Y=A
EN
1: Circuits & Layout
CMOS VLSI Design
Slide 19
Multiplexers
 2:1 multiplexer chooses between two inputs
S
S
D1
D0
0
X
0
0
X
1
1
0
X
1
1
X
1: Circuits & Layout
Y
D0
0
Y
D1
CMOS VLSI Design
1
Slide 20
Multiplexers
 2:1 multiplexer chooses between two inputs
S
S
D1
D0
Y
0
X
0
0
0
X
1
1
1
0
X
0
1
1
X
1
1: Circuits & Layout
CMOS VLSI Design
D0
0
Y
D1
1
Slide 21
Gate-Level Mux Design
 Y  SD1  SD0 (too many transistors)
 How many transistors are needed?
1: Circuits & Layout
CMOS VLSI Design
Slide 22
Gate-Level Mux Design
 Y  SD1  SD0 (too many transistors)
 How many transistors are needed?
20
1: Circuits & Layout
CMOS VLSI Design
Slide 23
Inverting Mux
 Inverting multiplexer
– Pair of tristate inverters
– Essentially the same thing
 Noninverting multiplexer adds an inverter
1: Circuits & Layout
CMOS VLSI Design
Slide 24
Transmission Gate Mux
 Two transmission gates
– Only 4 transistors
S
D0
Y
S
D1
S
1: Circuits & Layout
CMOS VLSI Design
Slide 25
4:1 Multiplexer
 4:1 mux chooses one of 4 inputs using two selects
1: Circuits & Layout
CMOS VLSI Design
Slide 26
4:1 Multiplexer
 4:1 mux chooses one of 4 inputs using two selects
– Two levels of 2:1 muxes
S1S0 S1S0 S1S0 S1S0
– Or four tristates
D0
S0
D0
0
D1
1
S1
D1
0
Y
Y
D2
0
D3
1
1
D2
D3
1: Circuits & Layout
CMOS VLSI Design
Slide 27
D Latch
 When CLK = 1, latch is transparent
– D flows through to Q like a buffer
 When CLK = 0, the latch is opaque
– Q holds its old value independent of D
 Transparent latch or level-sensitive latch
D
Latch
CLK
1: Circuits & Layout
CLK
D
Q
Q
CMOS VLSI Design
Slide 28
D Latch Design
 Multiplexer chooses D or old Q
1: Circuits & Layout
CMOS VLSI Design
Slide 29
D Latch Operation
1: Circuits & Layout
CMOS VLSI Design
Slide 30
D Flip-flop
 When CLK rises, D is copied to Q
 At all other times, Q holds its value
 Positive edge-triggered flip-flop, master-slave flipflop
CLK
CLK
D
Flop
D
Q
Q
1: Circuits & Layout
CMOS VLSI Design
Slide 31
D Flip-flop Design
 Built from master and slave D latches
Master
Slave
CLK
CLK
CLK
QM
D
CLK
QM
Latch
D
Latch
CLK
CLK
CLK
CLK
Q
CLK
1: Circuits & Layout
Q
CMOS VLSI Design
CLK
Slide 32
D Flip-flop Operation
Master on
Slave off
Master of
Slave on
1: Circuits & Layout
CMOS VLSI Design
Slide 33
Race Condition
 Back-to-back flops can malfunction from clock skew
– Second flip-flop fires late
– Sees first flip-flop change and captures its result
– Called hold-time failure or race condition
CLK1
CLK2
Q1
Flop
D
Flop
CLK1
CLK2
Q2
Q1
Q2
1: Circuits & Layout
CMOS VLSI Design
Slide 34
Nonoverlapping Clocks
 Nonoverlapping clocks can prevent races
– As long as nonoverlap exceeds clock skew
 We will use them in this class for safe design
– Industry manages skew more carefully instead
2
1
QM
D
2
2
2
Q
1
1
1
1
2
1: Circuits & Layout
CMOS VLSI Design
Slide 35