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Computer Memory
Storage
Decoding
Addressing
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Memories We've Seen
SIMM = Single Inline Memory Module
DIMM = Dual IMM
SODIMM = Small Outline DIMM
RAM = Random Access Memory
SDRAM = Synchronous Dynamic RAM
RDRAM = Direct Rambus DRAM
A type of SDRAM
Rambus = The developing company
ROM = Read Only Memory
Some Definitions
DRAM Comparison
Levels of the Memory Hierarchy
Part of The On-chip
CPU Datapath
ISA 16-128
Registers
One or more levels (Static RAM):
Level 1: On-chip 16-64K
Level 2: On-chip 256K-2M
Level 3: On or Off-chip 1M-16M
Dynamic RAM (DRAM)
256M-16G
Interface:
SCSI, RAID,
IDE, 1394
80G-300G
CPU
Registers
Cache
Level(s)
Main Memory
Farther away from
the CPU:
Lower Cost/Bit
Higher Capacity
Increased Access
Time/Latency
Lower Throughput/
Bandwidth
Magnetic Disc
Optical Disk or Magnetic Tape
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Memory Hierarchy Comparisons
Capacity
Access Time
Cost
CPU Registers
100s Bytes
<10s ns
Cache
K Bytes
10-100 ns
1-0.1 cents/bit
Main Memory
M Bytes
200ns- 500ns
$.0001-.00001 cents /bit
Disk
G Bytes, 10 ms
(10,000,000 ns)
-5
-6
10 - 10 cents/bit
Tape
infinite
sec-min
-8
10
Staging
Xfer Unit
faster
Registers
Instr. Operands
prog./compiler
1-8 bytes
Cache
Blocks
cache cntl
8-128 bytes
Memory
Pages
OS
4K-16K bytes
Files
user/operator
Mbytes
Disk
Larger
Tape
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Memory Arrays (Hierarchy)
Memory Arrays
Random Access Memory
Read/Write Memory
(RAM)
(Volatile)
Static RAM
(SRAM)
Dynamic RAM
(DRAM)
Mask ROM
Programmable
ROM
(PROM)
Content Addressable Memory
(CAM)
Serial Access Memory
Read Only Memory
(ROM)
(Nonvolatile)
Shift Registers
Serial In
Parallel Out
(SIPO)
Erasable
Programmable
ROM
(EPROM)
Queues
Parallel In
Serial Out
(PISO)
Electrically
Erasable
Programmable
ROM
(EEPROM)
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First In
First Out
(FIFO)
Last In
First Out
(LIFO)
Flash ROM
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Memory Comparisons
Non-Volatile Memories (ROM / Flash)

Floating-gate transistor
Floating gate
Gate
Source
D
Drain
G
tox
tox
n+
p
n+_
S
Substrate
Device cross-section
Schematic symbol
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6T SRAM Cell (6 transistors)

Cell size accounts for most of array size


6T SRAM Cell



Used in most commercial chips
Data stored in cross-coupled inverters
Read:



Reduce cell size at expense of complexity
bit
bit_b
Raise wordline
word
Read bit, bit_b (complement of bit)
Write:



Drive complementary data
onto bit, bit_b
Raise wordline
Bit lines overpower old data
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1-Transistor DRAM Cell



Write: Cs is charged or discharged by asserting WL
and BL
Read: Charge redistribution takes place between bit
line and storage capacitance
Voltage swing is small; typically around 250 mV
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Read-Write Memories (RAM)

Static (SRAM)





Data stored as long as supply is applied
Large (6 transistors/cell)
Fast
Differential
Dynamic (DRAM)




Periodic refresh required
Small (1-3 transistors/cell)
Slower
Single Ended
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Connecting Memory
Processor
Memory
k-bit
address bus
MAR
n-bit
data bus
MDR
Up to 2 k addressable
locations
Word length = n bits
Control lines
( R / W, MFC, etc.)
MAR = Memory Address Register
MDR = Memory Data Register
MFC = Memory Function Complete signal
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Memory Array Architecture


2n words of 2m bits each
If n >> m, fold by 2k into fewer rows of more columns
wordlines
bitline conditioning
bitlines
row decoder
memory cells:
2n-k rows x
2m+k columns
n-k
column
circuitry
k
n


column
decoder
2m bits
Good regularity – easy to design
Very high density if good cells are used
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Decoders

n:2n decoder consists of 2n n-input AND gates


One needed for each row of memory
Build AND from NAND or NOR gates
A1
A0
word0
word1
word2
word3
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Large Decoders

For n > 4, NAND gates become slow

Break large gates into multiple smaller gates
A3
A2
A1
A0
word0
word1
word2
word3
word15
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Column Circuitry

Some circuitry is required for each column



Bitline conditioning
Sense amplifiers
Column multiplexing
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Column Multiplexing


Recall that array may be folded for good aspect ratio
Ex: 2 kword x 16 folded into 256 rows x 128 columns


Must select 16 output bits from the 128 columns
Requires 16 8:1 column multiplexers
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Memory Timing: Approaches
DRAM Timing
Multiplexed Adressing
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SRAM Timing
Self-timed
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DRAM Timing
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Serial Access Memories

Serial access memories do not use an address





Shift Registers
Tapped Delay Lines
Serial In Parallel Out (SIPO)
Parallel In Serial Out (PISO)
Queues (FIFO, LIFO)
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Shift Register
Shift registers store and delay data
 Simple design: cascade of registers


Watch your hold times!
clk
Din
Dout
8
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Serial In Parallel Out

1-bit shift register reads in serial data

After N steps, presents N-bit parallel output
clk
Sin
P0
P1
P2
P3
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Parallel In Serial Out

Load all N bits in parallel when shift = 0

Then shift one bit out per cycle
P0
P1
P2
P3
shift/load
clk
Sout
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Queues
Queues allow data to be read and written at
different rates.
 Read and write each use their own clock, data
 Queue indicates whether it is full or empty
 Build with SRAM and read/write counters
(pointers)

WriteClk
WriteData
FULL
ReadClk
Queue
ReadData
EMPTY
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FIFO, LIFO Queues

First In First Out (FIFO)






Initialize read and write pointers to first element
Queue is EMPTY
On write, increment write pointer
If write almost catches read, Queue is FULL
On read, increment read pointer
Last In First Out (LIFO)


Also called a stack
Use a single stack pointer for read and write
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