Survey
* Your assessment is very important for improving the workof artificial intelligence, which forms the content of this project
* Your assessment is very important for improving the workof artificial intelligence, which forms the content of this project
Ramp Generator and Super Buffer/Driver Design Fukun Tang For psASIC Design Review July 1-2 2009 University of Chicago F. Tang ADC Architecture Sampling channel : ADC: Ramp Gen. : 4 Ramp Volt. Tc 125/Channel 1 Sampled Volt. Super Buffer/Driver: 4 To Sampling Cells MCP Cs DFF EN Counter 2GHz Clock Ramp Start Ramp Gen. & Buffers/Driver F. Tang Wilkinson ADC Core Schematic Diagram of Ramp Generator and Super Buffer/Driver F. Tang Schematic of Super Buffer/Driver Cc F. Tang Simulation of Super Buffer/Driver • Capable to drive 125 comparators (huge load) • Gian-1 Stable • Adequate bandwidth (slew rate and noise etc) • Linearity and dynamic range Compensation Cap = 2pf with 2pf load Compensation Cap = 1pf with 2pf load F. Tang Simulation Results of Super Buffer/Driver F. Tang Simulation Results of Ramp Gen. & Super Buffer/Driver Non Linearity = ~20%, It can be calibrated off-line F. Tang Summary Simple current source and low rail voltage presents big non-linearity on ramping current. Non-linearity can be calibrated off-line. Work need to be done: Layout Post layout simulation Minor tuning on gate parameters may be required after post layout simulation F. Tang Thank you for your review F. Tang