Download spice netlist

EMT 251
SPICE NETLIST
Introduction
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SPICE (Simulation with Integrated Circuits Emphasis)
General purpose circuit simulator which widely used in
microelectronics industry
Developed at University of California Berkeley
Many variants e.g. HSPICE, PSPICE etc.
Uses a simple netlist format for data input
Most manufacturers provide SPICE models as an
essential for CAD tool
Knowledge of various device parameters are essential
for performing detailed circuit simulations and for
optimizing design
Cont…
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SPICE had three built-in MOSFET models:
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Level 1 (MOS1) >> described by square-law currentvoltage characteristics
Level 2 (MOS2) >> detailed analytical MOSFET
model
Level 3 (MOS3) >> semi-empirical model
Recently, BSIM3 (Berkeley Short-Channel
IGFET Model) ver. has been added to allow
more accurate characterization of sub-micron
MOSFET characteristics
SPICE Netlist Flow Chart
Advantages
Improved memory utilisation
 Improved convergence for numerical
algorithms
 Improved accuracy
 Improved execution speed
 Can be used for mixed mode simulation
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Basic Concept
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Circuits for SPICE simulation are
described:
The elements of the circuit (voltage, current,
resistors, capacitors, transistors etc.)
 A list of the nets/nodes (can be assigned
names or numbers depending on the specific
software used)
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Example:
circuit’s element
list of nodes
Element Line Descriptions
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Voltage Source
Vxx +node -node DC value
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Current Source
Vxx +node -node DC value
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Resistor
Rxx node1 node2 value
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Capacitor
Cxx node1 node2 value
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Diode
Dxx +node -node model_name <area> plus other optional parameters
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Bipolar Transistor
Qxx collector base emitter <bulk> model_name <area> plus other optional parameters
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MOS Transistor
Mxx drain gate source bulk model_name <L=value> <W=value> <AD=value> <AS=value>
plus other optional parameters
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Note: parameters in <> are optional and not required for simulation.
Analysis Descriptions
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SPICE can perform a variety of types of analysis on a circuit:
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Transient Analysis
.TRAN TSTEP TSTOP <TSTART> <TMAX>
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TSTEP is the time step used between analysis points, and the
smaller the value is, the more resolution you will get in your
simulation. A typical value is 1nsec.
TSTOP is the time when you want your transient analysis to
stop. This value will depend on the frequency of your input
signal(s) and the time it takes for your circuit to produce its final
output.
TSTART is used if you want the analysis to start at some time
other than Time=0.
TMAX is used to set the largest step time that will be used. This
parameter is typically not needed.
Cont..
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DC Analysis
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Use a DC analysis if you want to view the response of the
circuit when a source (voltage or current) sweeps between
two DC values. The command and parameters are:
.DC Source_name START STOP STEP
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Source_name is the name of the source that will be swept.
START and STOP are the beginning and ending values of
the sweep.
STEP is the increment value used during the sweep.
Cont..
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AC Analysis
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sweep all AC sources across a range of
frequencies, use the .AC command.
.AC Lin/Dec/Oct N FSTART FSTOP
 FSTART
and FSTOP are the beginning and ending
frequencies of the AC analysis.
 Select either Lin, Dec, or Oct for a linear, decade,
or octave scaled sweep with N points analyzed.
SPICE Units
The default units for SPICE are volts, amps, ohms, farads, henries,
watts etc. You can specify values in decimal form, 0.0056, or
exponential form, 5.6e-3. SPICE also recognizes the following
abbreviations:
f
p
n
u
m
k
meg
g
t
E-15
E-12
E-9
E-6
E-3
E+3
E+6
E+9
E+12
femto
pico
nano
micro
milli
kilo
mega
giga
tera
For clarity you can add letters to the abbreviation as in 1U or
1UFARADS and both are read as the value 1e-6.. SPICE processes
the first letter after the number and ignores the rest.
SPICE Netlist for inverter
.global VDD GND
.connect GND 0
.lib /EDA/Mentor-training-ADK/technology/accusim/tsmc035.mod NOM
.probe tran V
.TRAN 0 400ns 1ns
.subckt circuit portin portout
MN1 DRAIN GET SOURCE BULK p L=0.4u W=1u
MN2 DRAIN GET SOURCE BULK n L=0.4u W=1u
.ends circuit
Format
.subckt inv in out
MN1 out in VDD VDD p L=0.4u W=1u
MN2 out in GND GND n L=0.4u W=1u
.ends inv
X13 portin portout circuit
VOL1 VDD GND DC 5V
VOL2 in GND PWL (0ns 0 100ns 0 101ns 5V 200ns 5V 201ns 0 300ns 0)
X13 in out inv
VOL1 VDD GND DC 5V
VOL2 in GND PWL (0ns 0 100ns 0 101ns 5V 200ns 5V 201ns 0 300ns 0)
.end
Format
Exercise (Write Netlist)
1.
2.
VDD
A
R1=1k
B
OUT
A
B
DC = 5V
R2=100
C1=100p
R3=100M
Solution
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Answer 1:
.global VDD GND
.connect GND 0
.lib /EDA/Mentor-training-ADK/technology/accusim/tsmc035.mod NOM
.probe tran V
.TRAN 0 1000ns 1ns
.subckt exercise1 A B OUT
MP1 node1 A VDD VDD pmos L=0.4u W=1u
MP2 OUT B node1 VDD pmos L=0.4u W=1u
MN1 OUT A GND GND nmos L=0.4u W=1u
MN2 OUT B GND GND nmos L=0.4u W=1u
.ends inv
X1 A B OUT exercise1
VOL1 VDD GND DC 5V
VOL2 A GND PWL (0ns 0 100ns 0 101ns 5V 200ns 5V 201ns 0 300ns 0)
VOL3 B GND PWL (0ns 0 100ns 0 101ns 5V 200ns 5V 201ns 0 300ns 0)
.end
Solution
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Question 2:
R1=1k
R2=100
R3=100M
C1=100p
DC = 5V
1
DC = 5V
R1=1k
2
R2=100
C1=100p
3
R3=100M
Solution
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Answer 2:
.global GND
.connect GND 0
.lib /EDA/Mentor-training-ADK/technology/accusim/tsmc035.mod NOM
.probe tran V
.TRAN 0 1000ns 1ns
V1
R1
R2
R3
C1
1 GND DC 5
1 2 1k
2 3 100
3 GND 100meg
2 GND 100p
V1 VDD GND DC 5V
.plot DC v(2,3)
.end
POP QUIZ
VDD
SL
A
A
MP2
MP1
MP3
MP4
MP6
B
B
Cin
MP5
F
Cin
A
MN2
MN5
B
SL
MN6
MN3
MN1
MN4
A
B