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A Fast Algorithm for
Power Grid Design
Jaskirat Singh
Sachin Sapatnekar
Department of Electrical and Computer Engineering
University of Minnesota
1
Introduction

Power supply network


VDD
Provides VDD and ground
to time varying current
sources (logic gates)
Power grid design issues
VDD , wire width , currents
 IR drop/ground bounce
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Signal integrity
 Gate delay


GND
Electromigration
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Mean failure time for wires
2
Introduction

Power grid design problem
Given an estimate of loading currents and power pad
positions
 Select a set of wire widths and pitches for the multiple-layer
network so that

Wire area is efficiently utilized
 Nodes (branches) satisfy voltage drop (current density) constraints
 Additional objectives of congestion minimization/shielding

3
Introduction
Power grid design methods
Explicit circuit simulation based method
•Detect and fix method
•Accurate Design
•Usually slow
Non-linear optimization based method
•KCL/KVL part of constraint set
•Approximations needed for efficiency
•May be inaccurate due to relaxations
4
Motivation

Notion of locality in power grid design

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“Fast Flip-chip Power Grid Analysis via Locality and Grid
Shell”, Eli Chiprout, ICCAD’04.
To construct local grids focus on details of local
regions. Abstract far away regions of the grid.
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Locality Example
Abstract
away far
off grid
regions

10 X 8 Grid
Each branch 1 ohm
Loaded with 1mA
VDD pads (1V )

Vspec = 0.9V


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Fix
Violations
Locally
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Locally Regular/Globally Irregular
High
High
Med
Low
High
High

Globally regular grid

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Globally irregular/locally regular grid


Med
Low
Over design of the grid
Efficient use of wire area
Reduced # of optimizable parameters
7
Power Grid Design Procedure
Recursive bipartitioning heuristic
based on notion of locality
Divide the chip area into partitions
Design local grids in the partitions
Abstraction of grids in partitions
Macromodeling technique by
M. Zhao et al, DAC’00
Coarse grid representation initially
Iterative refinement of grid
Post processing step to maximize
wire alignment
8
Recursive Bipartitioning Method


Divide and conquer approach
Solve a local power grid design problem in each step
2
4
1
2
3
k
3
5
K+1
2 -1
Vertical, horizontal partition wire
Active partitions
9
Recursive Bipartitioning Method
Level-1 Partition
Level-k Partition
Level-2 Partition
Level-2 Partition
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First level of partitioning
I  A V p  S

Construct macromodels for the two partitions
( A, S )
( A1 , S1 )
Port Nodes
( A2 , S2 )
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First level of partitioning



Stamp the macromodels in the global MNA system
Solve each partition by hierarchical analysis
For violations in a partition, fix it locally
( A2 , S2 )

( A1 , S1 )
( A2 , S2 )
M X b
M X b
Speed up in circuit analysis step


Use very thick wires for initial partition levels
In subsequent partition levels refine the grid by reducing the wire width
12
Second level of partitioning
( A3 , S3 )

Use the power grid constructed at the first level

Rip up the grid in left partition
Add a horizontal partition wire



Leave the grid in the right partition intact, seen as an abstraction
Construct a refined grid in the top-left and bot-left partitions by the
hierarchical design methodology
13
Second level of partitioning
γ

Requirements for power grid constructed in new active partitions

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IR drop and EM constraints met in the active partitions
Maintain correctness of the power grid in the right partition


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Solve new global system M X=b
Compare old and new port voltages of the right partition
If Max( New_port_voltage – Old_port_voltage) > є (e.g., 1% VDD)
 Power grid in right partition is disturbed
 Add more wires in the active partitions and repeat the design procedure
14
Recursive bipartitioning algorithm
Make
macro
( A1 , S1 )
Solve by hierarchical
analysis
( A2 , S2 )
Detect
violations
Make
macro
Decr width
by γ
Decr pitch
by β
Make next
partitions
Repeat
Check neighbor
port voltages
Decr width
Port voltage change > є ?
by γ
Make next
partitions
Done
Post processing to align wires
15
Recursive bipartitioning algorithm

A breakdown scenario

Make_macromodels( );
Solve_grid( );
If(violations in one or both partitions)
Decr wire pitch of violating partition;
If (Pitch of the active partition < min_pitch)
Min pitch violation;

Min pitch violation
Grid refinement doesn’t work
γ

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Check_neighbor_grids( );
If(port nodes of neighbor grids perturbed)
Decr wire pitch of active partition;


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Grids in neighboring partitions
disturbed
Can’t be fixed by adding wires
in active partitions
Traverse to the inactive
partitions and add more wires
Adversely affects the runtime
of the procedure
Empirically a rare event if
γ is [ 0.65,1 )
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Post processing step





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At the end of design the wires might be misaligned due to different wire pitches in
adjacent partitions
Superimpose a uniform and continuous virtual grid
Pitch of the virtual grid is chosen to be the minimum pitch of all partitions
Move the real power grid wires to the nearest vacant position on the virtual grid
Perform a complete simulation by hierarchical analysis after the wire movements
Add more wires if required on the virtual grid place holders
17
Experimental Setup

Input

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Floorplans with functional block current estimates
Power pad locations and number
Grids constructed for power delivery to 2cm X 2cm chip
Vdd=1.2V, Vspec=1.08 V
Sheet resistivity, current density, min pitch for 130nm tech
Flip-chip (FC)  400-600 power pads
Wire-bond(WB)200-300 pads located at the periphery
Initial wire width 60-100 µm, k=7 levels of partitioning
γ in (0.65,1] , β in (0.5,1], є=15mv
Output


A non-uniform power grid that meets the IR drop and EM constraints
Wire width at the end of design is 2-6 µm
18
Experimental Results


Ckt
# of
Blocks
pg-1
# of Nodes
( in millions)
Wire Area
Run Time
(10-2 cm2)
(sec)
FC
WB
FC
WB
FC
WB
17
1.56
1.63
8.12
8.52
443
661
pg-2
17
1.19
1.22
7.83
8.16
517
787
pg-3
12
1.26
1.38
7.21
7.54
653
839
pg-4
16
1.05
1.21
6.88
7.38
617
842
pg-5
20
1.22
1.34
7.04
8.06
572
805
pg-6
24
1.14
1.19
7.22
7.86
683
935
pg-7
20
1.64
1.70
8.52
10.22
431
692
pg-8
22
1.29
1.36
8.40
9.92
452
671
Power grids > 1M nodes designed in 7-12 mins for FC and 11-16 mins for WB
Wire bond designs are suboptimal due to absence of locality property
19
Experimental Results


Proposed method compared with a previous work
K. Wang and M. M Sadowska, “On-chip Power Supply
Network Optimization using Multigrid-based
Technique”, DAC’04
Multigrid method based on mapping from original
space to a reduced space
Multigrid
Reduction
Original
mesh
Reduced
mesh
Optimization
engine
Back
mapping
20
Experimental Results
% Saving in power grid wire area
1
0.98
0.96
0.94
0.92
0.9
0.88
0.86
0.84
0.82
0.8
Proposed Method
Multigrid Method
Ckt-1 Ckt-2 Ckt-3
Ckt-4 Ckt-5 Ckt-6
7%-12% reduction in wire area over the multigrid-based method
21
Experimental Results

Constraints in the multigrid-based method
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All rows (columns) of wires are constrained to have the
same width
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Wastage of wiring resources
Current Densities
High
High
Med
Low
22
Experimental Results
Runtime comparison of the two power grid design methods
1.15
1.1
1.05
Proposed Method
Multigrid Method
1
0.95
0.9
Ckt-1 Ckt-2 Ckt-3
Ckt-4 Ckt-5 Ckt-6
Runtime is of the same order for the two methods
23
Summary



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A novel and efficient power grid design procedure proposed
Use notion of locality in grid design
Accuracy is maintained by using circuit analysis step in the
inner loop
Circuit analysis is made efficient by the use of


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Grid abstractions
Coarse initial grid models followed by successive grid refinements
Considerably fast power grid design method with efficient
wire area utilization
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THANKS !!!
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