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TRIGGER DELAY 100µs Requirements • The trigger delay is a back-up system that generates an asynchronous dump trigger for MKD and MKB in case of problems with the synchronous dump trigger. • Design goals are to make a system that is stand-alone, simple and reliable. • Stand–alone means that the system is completely selfcontained. Its function is not affected by any external condition. • Simplicity means to minimise number of components for the critical part of the circuit. G. Gräwer AB/BT/EC LBDS Trigger Delay 2 Block diagram 230VAC 3U Eurochassis Trigger In VB Power supply B 24VDC VA Power supply A 24VDC Delay 100µs Interlock loop To 25 retrigger boxes 15 MKD and 10 MKB Error Warning Interlock Trigger Out To PLC G. Gräwer AB/BT/EC LBDS Trigger Delay 3 General description • The trigger delay generates an output pulse 100µs after the input trigger • The trigger delay unit has got two internal 24V power supplies. If one of them fails it continues working with the other one and a warning signal is generated for the PLC. The faulty power supply should be replaced at the next possible occasion. • If both power supplies fail or in case of mains failure supply voltage is maintained by internal capacitors. The unit still remains operational for several minutes (up to 30min). • In case of a fault in the trigger delay unit the interlock circuit generates an error signal for the PLC. • There are three possible faults that can cause an error: • Input disconnected. • Output disconnected. • Low voltage of oscillator capacitor. G. Gräwer AB/BT/EC LBDS Trigger Delay 4 G. Gräwer AB/BT/EC VCAP LBDS Trigger Delay BZX55C12 220n C5 47 T1 R6 D24 D7 D4 BZX55C15 BZX55C15 D25 1k, 1W R5 2µ2, 35V 1k2, 1W ZKB T60403D4097-X054 1N4151 D16 22n 100 D9 100k C8 R4 1N5060 1k C16 VB R16 47n R43 1N5060 R17 1N4151 Trigger in 100 D15 VT R15 D3 10µ C3 1N4151 100, 1W 350µ L1 D5 R1 710n C7 15 27k 1N4151 BYV27-200 C6 R9 D2 2N2324 1N4151 D14 Q1 R13 470 220 32Z R14 1N4151 68 R12 D1 VT D11 VB 1N4151 D12 R11 VA 1N4151 1N4151 1N4151 D13 D10 24V in 30Z YELLOW D8 Trigger Schematic of trigger delay VA C1 10m, 40V 1:1:1 Trigger out 4Z 6Z 8Z M1 IRFF130 5 Principle of operation Main circuit • The trigger delay circuit is completely analogue. The semiconductors used in the critical part of the circuit are one thyristor Q1, one MOSFET M1 and several diodes. The delay time is determined by one period of an LC oscillator L1 and C7. • A trigger pulse at the input triggers Q1. For the first half of the oscillation the current flows through Q1 until the zero crossing. For the second half of the oscillation the current changes direction and flows through the diode D14 while Q1 is turned off. At the end of the oscillation Q1 blocks the voltage VT. The rising edge of VT turn on M1 and this generates the output trigger pulse. G. Gräwer AB/BT/EC LBDS Trigger Delay 6 Principle of operation Interlock circuit • The Interlock circuit monitors the internal 24V supply voltages, the voltage VT at Q1 and the interlock loop. • If one of the supply voltages fails a warning signal is generated. • If VT stays low for too long, the interlock loop is broken or the input is disconnected an error signal is generated. The cable from the trigger delay unit to the retrigger boxes contains two pairs of wires. One for the trigger signal and one for the interlock loop. At the end of the cable the interlock loop must be shorted. This is to make sure that the trigger cable is properly connected. G. Gräwer AB/BT/EC LBDS Trigger Delay 7 Waveforms Oscillator current Oscillator Voltage Trigger in Trigger out VT G. Gräwer AB/BT/EC LBDS Trigger Delay 8 Input fault detection Trigger line with fault detection +12V C1 C2 50W coaxial cable OUT IN 220k 2k R4 Trigger pulse on cable with offset voltage R3 47n R2 47n OUT 50 IN Trigger Receiver 2k R1 Trigger Driver Voffset C3 1n IN Trigger pulse at driver output. Rise time <100ns OUT Schmitt trigger monitors offset voltage. Error if offset voltage below threshold. Time constant R4, C3 >>time constant trigger pulse The voltage divider R1, R2 generates an offset voltage that is monitored by the schmitt trigger on the receiver side. If the driver is not working or the cable is broken the offset voltage is low or zero and an error signal is generated. G. Gräwer AB/BT/EC LBDS Trigger Delay 9 VT VC R20 20M 2M2 R21 R19 220k VD 2k2 R18 Trigger Schematic of interlock circuit CD4093B 2 IC1:A Interlock loop VD & IC1:B 5 6 CD4093B 2n2 R22 11M C10 1n C9 3 & 1 R23 14Z 1k, 1W 16Z 1N5060 D18 2µ 1M C12 1k, 1W VD D17 R25 VB R24 4 VA VD VD 8 R33 11 & 9 & Q8 R36 2N2219A 16 4 K2 1N4151 8 D23 6 RED 1 D22 1N4151 K1 R42 680 R40 10k D21 GREEN 1k5, 1W R41 680 10k GREEN 1k5, 1W 220n RED D20 R39 110k C15 1k2, 1W IC1:C 2N2219A 110k R38 BZX55C12 VD 4k7 Q7 R35 220n R37 R30 R34 10 VD 4k7 IC1:D C14 2k2 Q5 BC107B CD4093B 12 VC D19 R32 Q6 2N2905A Q3 BC107B CD4093B 13 VC 22k 2k2 R29 VC Q4 2N2905A 22k R31 R28 200k 200k R27 R26 VC 10n C13 1N5060 1 16 6 8 4 24Z 26Z 14 100n C11 28Z IC1 18Z 20Z 7 22Z G. Gräwer AB/BT/EC Error LBDS Trigger Delay Warning 10 Trigger delay PCB G. Gräwer AB/BT/EC LBDS Trigger Delay 11