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3D Simulation and Analysis of
the Radiation Tolerance of
Voltage Scaled Digital Circuits
Rajesh Garg
Sunil P. Khatri
Department of ECE
Texas A&M University
College Station, TX
1
Outline

Background and Motivation

Previous Work

Simulation Setup

Results and Discussions

Circuit-level hardening guidelines

Model for Charge collected

Conclusions
2
Charge Deposition by a
Radiation Particle




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Radiation particles - protons, neutrons, alpha particles and heavy
ions
Reverse biased p-n junctions are most sensitive to particle strikes
Radiation
Charge is collected at the
Particle
drain node through drift
and diffusion
VDD
G
Results in a voltage glitch
S
D
at the drain node
_ n+
n+
Depletion
+
System state may change
Region
_+ _+ E
if this voltage glitch is
_
+ E VDD - Vjn
_
captured by at least one
+
_
memory element
_ +
+
_
 This is called an SEU

May cause system failure
+
p-substrate
B
3
Radiation Strike Model

Charge deposited (QD) by a radiation particle is given by
QD  0.01036  L  t
where: L is the Linear Energy Transfer (MeV-cm2/mg)
t is the depth of the collection volume (mm)

A radiation particle strike is modeled by a current
pulse as
Qcoll
t / t
iseu (t ) 
(e  t / t a  e b )
(t a  t b )
t
Q = 0.1pC
a = 150ps
tb = 50ps
where: Qcoll is the amount of charge collected
(assumed Qcoll = QD in worst case analysis)
ta is the collection time constant
tb is the ion track establishment constant

The radiation induced current always flows from n-diffusion
to p-diffusion
4
Radiation Particle Strikes



Radiation particle strike at the output of INV1
Implemented using 65nm PTM with VDD=1V
Radiation strike: Q=100fC, ta=200ps & tb=50ps
Models Radiation
Particle Strike
5
Motivation

Modern VLSI Designs


Single Event Upsets (SEUs) or Soft Errors



Vulnerable to noise effects- crosstalk, SEU, etc
Troublesome for both memories and
combinational logic
Becoming increasingly problematic even for
terrestrial designs
Applications demand reliable systems

Need to efficiently design radiation tolerant
circuits
6
Motivation

Power is becoming a major issue


P  Pdyn  Plkg
Both Pdyn and Plkg decrease atleast quadratically
with decreasing supply voltages



Low power/energy solutions are desired for SoCs,
microprocessors, etc
Decrease the supply voltage in the non-critical parts
Dynamic voltage scaling (DVS) is extensively
used to meet variable speed/power requirements
Sub-threshold circuits are also becoming popular
to implement extremely low power systems

Useful for applications which can tolerate large delay
7
3D Simulations of Radiation Strikes


Reliability of DVS and sub-threshold circuits important
for the reliability of VLSI systems
Need to analyze the effects of radiation strikes on such
circuits

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SPICE cannot be used for this analysis



Harden the circuits based on the results of this analysis
The effect of a radiation particle strike is modeled, not the
radiation strike itself
3D simulations of radiation particle strikes in DVS and
sub-threshold circuits need to be performed for an
accurate analysis (for example, obtain the fraction of QD
that is collected)
We performed 3D simulations of a radiation strike in an
inverter implemented using a 65 nm technology for
different supply voltages (from nominal value to <VT)
8
Previous Work

Palau et al. 2003 studied radiation-induced transients
and SER in SRAMs using a 3-D device simulation tool



Irom et al. 2002 performed an experimental study of the
effects of radiation strikes in PowerPC microprocessors



Studied effects of different radiation particle tracks on SER
Effect of voltage scaling on SER not studied
Processors were implemented using 0.18 mm and 0.13 mm
technologies
Reduction of core voltage from 1.6 V to 1.3 V had little effect on SER
Flament et al. 2004 experimentally evaluated the
sensitivity of various commercial SRAMs to radiation
strikes for different supply voltages (VDD)

SRAMs implemented using technologies ≥ 0.18 mm with VDD ≥ 1.5 V
9
Previous Work

Hazucha et al. 2000 obtained an empirical model for
estimation of SER for a 0.6 mm CMOS process as a
function of the critical charge and VDD through
experiments and simulations



A latch with diodes was used for SER measurements for VDD ≥
2.2V
3D simulations of a radiation particle strike in diode were
performed
The above work was conducted in older technologies


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No circuit level hardening guidelines were proposed
DSM technologies and voltage scaling exhibit different behavior
Cannot be used to predict susceptibility of DSM devices at lower
VDD
10
Simulation Setup
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Implemented in a 65nm bulk technology
A radiation particle strike at the drain of
the NMOS of INV
in
Simulated using Sentaurus-DEVICE Set to GND

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
INV
3D Device Model
2X, 4X and 15X
LET of heavy ions considered are 2, 10 and 20 MeV-cm2/mg


out
3 different INV sizes were simulated


To simulate sub-threshold and DVS circuits
|VT| of the PMOS transistor is 0.365V
Radiation Particle
Cload
Mixed-level device and circuit simulator
Varied VDD from 0.35V to 1 V
SPICE Model
To simulate low, medium and high energy particle strikes
Also simulated 4X INV with a radiation strike of LET = 2 & 10
MeV-cm2/mg (with different load capacitances) and VDD = 1V

To analyze the effect of loading on the radiation susceptibility of the INV
11
NMOS Device Modeling



Constructed NMOS transistors using
Sentaurus-Structure editor tool
Gate length 35nm, Tox = 1.2nm
spacer width = 30nm
A heavy ion strikes at the center of
the drain
Heavy Ion
Punch through
Halo implants V impant
T implant
in
out1
Cload
INV
3D Device Model
Well Contact
G
D
SPICE Model
S
12
NMOS Device Characterization



Characterized the
NMOS device using
Sentaurus-DEVICE
Width = 1mm
Good MOSFET
characteristics
13
Results and Discussions


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Radiation strikes at the output of 4X INV for VDD = 1V
Low energy particle is also capable of producing significant
voltage glitch
For LET = 2 the drain current looks like double exponential


Most of the charge gets collected by drift process
For larger LET values, there is a plateau

Heavily doped substrates demonstrate charge collection due to both drift
and diffusion processes– in DSM processes, substrates are heavily doped
14
Results and Discussions





Q

I
 dt
A 
 (VDD  V (out ))  dt
collbiased electric
D
Reverse
field is present forVG
shorter duration in small devices
t t1
t t1
Lower drain area – less charge is collected through diffusion
G1 – If we upsize a gate to harden it, a higher value of Qcoll should
be used



O1 – Small devices
collect less charge compared to large devices
NMOS
Extremely important for low voltage operation
O1.1 – For low energy strikes, Qcoll remains roughly constant
across different gate sizes for nominal voltage operation
15
Results and Discussions

O2 – For low energy strikes,
wide devices collect almost the
same amount of charge across
different VDD values


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Reverse biased electric field is
present for a long duration
Most of the charge gets collected
within a few picoseconds after
the strike
G2 – For SPICE simulations and circuit hardening against low
energy strikes, it is safe to assume that Qcoll remains constant
across different VDD values for wide devices
O2.1 – Qcoll reduces with decreasing VDD


At lower VDD, the electric field is weaker than at higher VDD
At higher VDD, the PMOS device is stronger hence, reverse biased
electric field is present for a long duration
16
Results and Discussions

O3 – The effect of radiation strikes
becomes severe for VDD < 0.6V

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G3 – DVS should scale VDD to 2VT
(~60% of nominal value)

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The PMOS which is primarily
responsible for recovery becomes
weaker at lower VDD values
A circuit should be hardened at the
lowest operating voltage against charge collected at that voltage
Sub-threshold circuits & circuits with VDD < 2VT need aggressive protection
4X INV, VDD = 1V varying Cload
O4.1 – For medium or high energy
strikes, area of voltage glitch
increases with increasing Cload


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Voltage glitch magnitude roughly
independent of Cload
Cload ↑ => recovery time ↑
Against common belief
17
Results and Discussions

O4.2 – For low energy strikes,
increasing Cload improves the
radiation tolerance of INV

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Magnitude of the voltage glitch
reduces with increasing Cload
Difference in magnitude is more
for low energy strikes
PMOS has to recover a lower voltage swing

O4.3 – Qcoll increases with increasing Cload

G4 – Cload should be kept low in circuits operating in high
energy radiation particle environments


Contrary to conventional wisdom
For low energy radiation environments, Cload should be kept high
18
Model for Charge Collected

Qcoll heavily depends upon VDD, LET and gate size

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For SPICE level simulations and circuit hardening, worst case
Qcoll is usually used
May lead to pessimistic designs if this approach is used for
hardening DVS circuits
Need accurate models for Qcoll to improve the accuracy
of SPICE simulations

We propose one such model
M
Qcoll
 min( K MAX  LET , KQW b1VDD b2 LET b3 )



KMAX .LET – maximum amount of charge that can be collected.
KMAX is obtained from 3D simulations at nominal VDD
The second term is obtained by curve fitting to the Qcoll
obtained from 3D simulations
Parameters of this model be added to SPICE model cards for
MOSFETs
19
Model for Charge Collected

Curve fitting was performed for VDD = 0.6V to 1V

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Applicable to circuits employing DVS
For medium and high energy particle strikes – hardening
needs to be performed against such particles
KMAX = 0.8, KQ = 16.54 fC, b1 = 0.704, b2 = 0.9 and b3 = 0.664
Avg. Error is just 6.3%
For low energy strikes,
Qcoll remains almost
constant
For sub-threshold
circuits, it is difficult to
find an accurate model

Charge collection
efficiency is very low
20
Conclusions


DVS and sub-threshold circuits are increasingly used
in VLSI systems
Important to analyze the effects of radiation particle
strikes in these circuits



Performed 3D simulations of a radiation particle strike
in an INV with DVS and for sub-threshold operation
Made several observations which are important to
consider during radiation hardening of these circuits


Harden the circuits based on this analysis
Also proposed several guidelines for radiation hardening
Proposed a model for Qcoll to improve accuracy of
SPICE simulations – small error of 6.3%
21
Thank You
22
Backup Slides
23
Layout Guidelines

In DSM technologies, a significant amount of charge is
collected through diffusion
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Reduce the drain-substrate junction area
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Depends upon the drain-substrate junction area
Share output diffusion node
Not always possible
SplitDone big device into 2 smaller devices and connect
them in parallel
G1



G
G
G
G
S G SD G
S
G2
D
S
G
S
S
D
S
S
S
D
S
S G distance
SD G S (d) apart from each
Place them a certain
1
2
D2 G S1
1
2
other
S
When one transistor get struck by a radiation strike,
the other collects very little charge
Simulated INV of different sizes with
D G S
the NMOS transistor implemented in
this manner
d
D G S
24
Layout Guidelines

Considered vertical and angled strikes – angled towards the
second transistor
45o Angled Strike
Vertical Strike
Single
Device
4X LET=10
33.2
4X LET=20
45.8
8X LET=10
53.7
8X LET=20
78.1
15X LET=10 70.7
15X LET=20 123.7



d (mm)
2.1
4.2
30.1 30.0
39.3 39.2
48.9 48.5
67.7 67.5
60.9 60.3
109.5 108.7
% Red
d = 4.2
Single
Device
9.75
14.43
9.65
13.56
14.72
12.12
29.6
42.3
45.7
69.4
54.6
103.2
d (mm)
2.1
30.1
42.1
47.2
71.5
58.7
109.6
4.2
27.9
37.1
43.5
62.6
53.1
96.5
% Red
d = 4.2
5.74
12.29
4.81
9.80
2.75
6.49
Vertical strike is the worst case strike for a single device
Qcoll can be reduced by up to 14.5%
If d is small (< 2 mm) then Qcoll is higher for angled strikes
compared to vertical strikes (not shown) – use single device
25
Standard Cell Layout Guidelines

Preference 1 – Reduce the output diffusion area by
sharing if possible

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Preference 2 – Split devices, separate them
by d ≥ 4 mm and connect them in parallel
For a 65 nm n-well process

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Not applicable to devices connected in parallel
PMOS devices collect less charge compared to
NMOS devices because
VDD
of lower collection
volume
P Device
NMOS need to be 2.6
mm
separated from
n-well
each other by ≥ 4 mm
This helps reduce
Qcoll by 10-14%
VSS
N Device
n-well
P Device
VDD
P Device
n-well
N Device
VSS
VSS
N Device
26