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Power Optimization
in
Low-Voltage High-Speed
High-Resolution
Pipelined ADCs
Hassan Sarbishaei
Ehsan Zhian Tabasy
Tahereh Kahookar Toosi
Reza Lotfi
Email: {hsarbishaei, ezhian, tktoosi, rlotfi}@ieee.org
Integrated Systems Lab.
Dept. of Electrical Engineering,
Ferdowsi University of Mashhad
Mashhad, I.R.Iran
August 2006
Power Optimization in Low-Voltage High-speed
High Resolution Pipelined ADCs
Abstract
► LOW-POWER
design of low-voltage high-speed
high-resolution A/D converters is presented. By
expressing the total current consumption of the ADC as
well as the ADC noise power as functions of the stage
resolutions, the stage capacitors and the compensation
capacitors of the cascode-compensated opamps, all
those parameters are optimally determined in order to
minimize power consumption for a definite budget for the
noise power. In this methodology, the small-signal settling
is considered as well as the large-signal settling. Besides,
the contribution of the comparators is considered in the
entire ADC current consumption. At last two poweroptimized pipelined ADCs utilizing the proposed and
conventional design methods are presented and
compared in 0.18µm CMOS technology with 1.2V supply
voltage. Considerable reduction in power consumption is
achieved.
Sarbishaei, Zhian, Toosi, Lotfi
August 2006
2
Power Optimization in Low-Voltage High-speed
High Resolution Pipelined ADCs
Power Optimum Compensation of
Fast-Settling Opamps
I i ,opt 
Veff ,i
VFS CC 
W
 1 
.
tS 
(1  2 2 ) 2fVFS



I t ,opamp  2( I i  I c  I a )  I bias  I cmfb
VDD
Mlu
Ii
Ml
Mc
Vout+
CL
Vout-
Vin+
CC
Vin-
Mlc
Ma
VCMFB
Mtail
Mld
g mc  n (2   ) (C1 
g mi
C
 W
 c
f 1  2 2 t s
g ma
CC
Ia
CL
Ic
Cload Cc
)
Cload  Cc
 Cload 
(1  2 2 )


nC2  1 
( 2   )
CC 

Sarbishaei, Zhian, Toosi, Lotfi
August 2006
3
Power Optimization in Low-Voltage High-speed
High Resolution Pipelined ADCs
Pipeline Structure
I residuestage  It ,opamp  (2m1  2) I comp
Analog
Input
Front-End
SHA
Stage #1
(CU1)
m1+1
Back-End
2-Bit
Flash
Stage #2
(CU2)
2
m2+1
Digital Error Correction
N-Bits
Digital Output
V
2
ni ,T
V
k
2
n,S / H

j 1
V 2 n, j
j 1
 Gi
2
i 1
V
2
n, j
 2 F (2   )(1  2 2 ) 2   m j
2 m j
 kT 


.(2

.2
)


2
2 2
op
 3 Cc (1  2    ) CF 
Sarbishaei, Zhian, Toosi, Lotfi
August 2006
4
Power Optimization in Low-Voltage High-speed
High Resolution Pipelined ADCs
Proposed Methodology
Desired SNR
Optimization
Program
Ii, CC, CF
HSPICE
Optimized Circuit
► TOTAL
input-referred
noise can be stated as a function
of opamp parameters, CF, CC and
each stage resolution. These
parameters should be chosen in
a way that meets noise constraint
(predefined SNR), while achieving
minimum power consumption.
► USING
an optimization
program, e.g. MATLAB, the
optimum
values
of
these
parameters can be found. Finally
with the aid of a circuit simulator,
e.g. HSPICE, the total ADC
utilizing these parameters is
simulated.
Sarbishaei, Zhian, Toosi, Lotfi
August 2006
5
Power Optimization in Low-Voltage High-speed
High Resolution Pipelined ADCs
Dependency of Pdiss on
ADC Parameters
► Pdiss vs. SNR
► Pdiss vs. Supply Voltage
SNR  cte .
V sup V FS

2
 v n 
 
 C  I  Pdiss 
► Pdiss vs. Sampling Rate
I t ,opamp 
k
ts
 I t , ADC 
k
 k f s
ts
Sarbishaei, Zhian, Toosi, Lotfi
August 2006
6
Power Optimization in Low-Voltage High-speed
High Resolution Pipelined ADCs
Simulation Results
Specification
Conventional
Methodology
Proposed
Methodology
SNDR (dB)
68.8
67.6
SFDR (dB)
71.1
71.4
ENOB (bit)
11.13
10.93
Power Dissipation (mW)
60
39
VDD (V)
1.2
1.2
VFS (V)
0.8
0.8
Parameters
Stage #1
Stage #2
Stage #3
Effective Resolution
(bit)
2
1
1
Unit / Compensation
Capacitor (pF)
(Proposed ADC)
4.2 / 3.23
1.42 / 3.46
0.28 / 0.9
Unit / Comp.
Capacitor (pF)
(Conventional ADC)
1.8 / 3.86
1 / 2.27
1 / 2.27
Sarbishaei, Zhian, Toosi, Lotfi
August 2006
7
Power Optimization in Low-Voltage High-speed
High Resolution Pipelined ADCs
Conclusion
► AN
effective yet simple and general design
methodology for power optimization in pipelined
ADCs is presented. The effectiveness of proposed
method over conventional optimization methods is
illustrated and finally, two design examples with the
same ADC specifications are simulated using
HSPICE to show the advantage of proposed
method. Simulation results show about 33%
decrease in total power consumption of proposed
ADC design compared to exemplified conventional
method.
Sarbishaei, Zhian, Toosi, Lotfi
August 2006
8