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Basic digital logic
J. Christiansen,
CERN - EP/MIC
[email protected]
General digital functions
Analog
ADC
Logic
Memory
DAC
Analog
Any digital function can be made from this structure
• Logic: Logical operations
– And, Or, Additions, Multiplications, Divisions, etc.
• Memory: Storage of variables and state
– Latch, Flip-Flops, registers, register files, SRAM, DRAM, ROM, etc.
Mixed signal design:
Both digital and analog functions on same IC / board
J.Christiansen/CERN
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Logic
Logic built from basic building blocks: Gates
Name
Function
Truth table
a
And
axb
a+b
0 1
0
0 0
1
0 1
a
Or
b
b
Symbol
0 1
0
0 1
1
1 1
a
b
a
b
a
Inversion
a
0
1
1
0
a
Others: Nand, Nor, Exclusive or, Multiplexer, Tristate, Full adder, Buffers, etc.
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Memory elements
Storage of a logic value for a give time period
Latch
D L Q
0 1 0
1 1 1
Flip-Flop
D C Q
D Q
L
X 0 Q
Level sensitive
D
0
0
1
1
X
Q
Q
Clock
D Q
L
D Q
L
Master – slave
latch
Edge sensitive
Memories
Address
Rd/wr
Decoding
Memory
array
Address decoding normally
divided in row and collumn
decoding
Data
RAM:
SRAM:
DRAM:
FLASH:
ROM:
PROM:
EPROM:
EEPROM:
DPM:
FIFO:
Random Access Memory
Static RAM
Dynamic RAM
“Permanent” RAM (no power needed)
Read Only Memory
Programmable ROM
Erasable PROM (with UV light)
Electrical Erasable PROM
Dual Port Memory
First In - First Out
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Logic optimization
• Reduction of logical expressions:
(~ = inversion)
– a x (b x c) = (a x b) x c = abc; a + (b + c) = (a + b) + c = a+b+c
– a + ~a = 1; a x ~a = 0
– a x (b + c) = ab + ac; a + (b x c) = a + bc (no reduction)
– ~(a + b) = ~a x ~b; ~(a x b) = ~a + ~b
Eg. ~a~b~c~d + ~ab~c~d = ~a~c~d x ( ~b + b ) = ~a~c~d x ( 1 ) = ~a~c~d
Heavy and tedious
• Reduction using graphical Karnough maps
–
–
Basic product terms:
~a~b~c~d + ~ab~c~d + ~ab~cd + ~abc~d + abcd + abc~d + a~bcd + a~bc~d
Reduced expression:
~a~c~d + ~ab~c + ac + bc~d = ~a~c x (~d + b) + c x (a + b~d)
Quick and elegant,
but for more than four variables it gets complicated
• Today: Logic synthesis
Only one bit changing
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c,d
a,b
00
01
11
00
1
1
0
01
0
1
0
11
0
0
1
10
0
1
1
10
0
0
1
1
Alternative:
bc~d or
~ab~d
5
Which gates are really needed ?
• How many different types of gates are needed to
implement any given logical function ? :
Inv
Memory elements can
also be made from this
And
Or
So why is this not used in practice ?
Too slow or too large area
Different drive capabilities also needed (buffers)
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Implementing logic with memories ?
• RAM or ROM can be used to implement logic
operations: Look Up Table (LUT)
Inputs
Logic
Output
Map any given combination into required output
Address
(input)
--0000
--0001
--0010
--0011
--0100
---------1111
Data
(output)
0
0
1
1
0
0
Address decoding logic + memory array
used to implement required function
For most applications Look up tables
not efficient (size and speed)
Special applications:
Special encoders/decoders
Programmable logic in FPGA’s
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Timing of digital circuits
Gates
Gate delay depends on:
Delay
Load
Type of gate
Number of inputs
Which input
Transition ( 0 -> 1 or 1 -> 0 )
Output load
Input slew rate
Temperature
Supply voltage
Process parameters
Technology
Sequential circuits
Clock
D
Q
Data
Timing
requirements
Clock
Setup: Input data must have stabilized certain time before clock
Hold: Data must not change within certain time after clock
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Timing examples
• Data arriving too late (too long logic delay)
D
Logic
Q
D
Clk
Q
Q
Logic delay
Clk
D
• Data arriving too early (clock skew problem)
Clk1
D
Clk
Q
D
Q
D
Flip-flop delay
Clk2
delay
• Asynchronous input signal (meta-stability problem)
Data from
asynchronous
system
D
Q
Delay
Sample point
Output finally
resolves to 0 or 1
Clk
Sample point
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Wires also have delays
• Capacitive loading of gate
(affects gate delay but can not be considered a wire delay)
• Propagation delay because of distributed L-C
– Wire has delay.
– Wire has characteristic impedance which may cause reflections.
– Normally not important inside chips but must be taken into account for
signal exchange between chips.
– If wire resistance also signal attenuation
Z
• R-C delays
– Thin wires have resistance and capacitance
– Gives wire delay
Reduces signal slew rate
Complicated delay calculation for wire networks
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Logic values
• Digital logic only works with Logic 0 and Logic 1
• Logic values represented by voltages
Output
+V
Input
+V
"1"
VOH
Noise Margin
High
VIH
Undefined
region
Noise
Crosstalk
Voltage drops
VIL
Noise Margin
Low
VOL
"0"
0
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0
11
State machines
• Used to go through sequence of events
based on inputs. State evaluation/change
every clock cycle.
• Best represented by state transition
diagrams.
• Implemented with state memory (flipflops) and state transition logic.
• Different encodings:
– Binary ( 000, 001, 010, 011, 100, )
– Gray code
Only one bit changes in any state transition
– One hot ( 001, 010, 100)
A
B
C
E
Clock
Inputs
State
Transition
logic
One and only one bit actively set (fast)
State
register
0
– Counters are a type of state machine with
simple algorithmic state transitions.
1
7
2
6
Counter
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D
Reset
5
4
3
12
Pipelining
• A Pipeline is used to increase operating speed of a digital circuit:
– Increases operation frequency
– Increases Latency (slightly)
tstor
tlogic
Storage
Logic
A
B
C
D
F1 = 1 / ( tlogic + tstor )
Latency1 = tlogic + tstor
Clock
Logic
D
Storage
Logic
C
Storage
Logic
B
Storage
Storage
Logic
A
F2 = 4 x F1
Latency2 = Latency1 + 3x tstor
Clock
Wave pipelining: Use delays as short term data storage
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Data processing
• In data processing applications a separation is
normally made between the real data processing and
the control of the processing.
– Data path:
Data exchange (data busses, data multiplexers, etc.),
Data storage (memory, pipeline, register file, etc.),
Data processing ( additions, multiplications, shifts, etc.)
– Control:
State machines that determines the control of the of the data path
Command
Status
Control
Unit 1
Unit 3
Unit 2
Unit 4
Register
file
Data path
Address generation path
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Data path control
• State machines (used in hardwired RISC processors)
Command
A
A
B
B
C
C
D
D
E
E
B
B
B
• Micro code (used in CISC processors)
Address
Command
Data
(Strongly simplified)
Micro code memory
Clock
Data path status
Data path control
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Digital implementation
Type
Year
Comment
Transistors
50
Descreete logic
60 - 80
(still used for RF and power)
TTL, FAST, ECL, NMOS, CMOS
PAL
70 - 80
Programmable, Simple functionality
PLD
80 - 90
Programmable, Limited functionality
CPLD
90 - ?
FPGA
90 - ?
Programmable, Complex logic
(Re)-Programmable, Very complex logic,
Cheap development, Limited large scale production cost
ASIC
80 - ?
Very high performance, Very large complexity,
Expensive development, Cheap large scale production
DSP/processor
80 - ?
Large flexibility, Data processing, Low–high performance
PAL: Programmable Array Logic
PLD: Programmable Logic Device
CPLD: Complex Programmable Logic Device
FPGA: Field Programmable Gate Array
DSP: Digital Signal Processor
ASIC: Application Specific Integrated Circuit
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IC Technologies
• Bipolar:
– High speed, Good analog performance, Limited integration
• NMOS:
– First MOS ( Metal Oxide Semiconductor ) technology
– Limited performance, High static power, Limited integration
• CMOS
–
–
–
–
–
Complementary MOS with zero static power
Very high integration
Very high performance in modern CMOS
Frequent introduction of improved technologies (every 2-3 years)
Other improvements:
• BiCMOS: Both Bipolar and CMOS on same chip
• SOI (Silicon on Insulator): Isolated devices and lower parasitic capacitances
• SiGe (Silicon Germanium): Improved transistor speed by incorporating Ge.
• Exotic: GaAs, HEMT,
– Very high speed ( RF, High speed telecommunication, etc.)
– Low integration, Low yield
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All this is just “simple” binary thinking
There are only 10 types of people in this world:
Those who understand binary
And those who don’t
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