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Digital Integrated
Circuits
The Inverter
Inverter
Voltage Transfer
Characteristic
Inverter
The CMOS Inverter: A First Glance
V DD
V in
V out
CL
Inverter
PMOS Load Lines
V
in
=V
DD + VGSp
I Dn = - I
Dp
Vout = V + VDSp
DD
I
I
Dn
I Dp
Dn
V
V =0
in
V
V =1.5
in
V
V
V
GSp
GSp
V
DSp
=-1
=-2.5
V
=V
+V
in
DD GSp
I
=-I
Dn
Dp
in
in
=0
=1.5
V
DSp
V
out
=V
DD
+V
DSp
Inverter
out
CMOS Inverter Load Characteristics
ID n
PMOS
Vin = 0
Vin = 2.5
Vin = 0.5
Vin = 2
Vin = 1
Vin = 1.5
Vin = 1.5
Vin = 1
Vin = 1.5
Vin = 2
Vin = 2.5
NMOS
Vin = 1
Vin = 0.5
Vin = 0
Vout
Inverter
CMOS Inverter VTC
NMOS off
PMOS res
2.5
Vout
2
NMOS s at
PMOS res
1
1.5
NMOS sat
PMOS sat
0.5
NMOS res
PMOS sat
0.5
1
1.5
2
NMOS res
PMOS off
2.5
Vin
Inverter
Switching Threshold as a function
of Transistor Ratio
1.8
1.7
1.6
1.5
M
V (V)
1.4
Idn(VM)=Idp(VM)
1.3
1.2
1.1
1
0.9
0.8
10
0
10
W /W
p
1
n
Inverter
Switching Threshold as a function
of Transistor Ratio
1.8
1.7
1.6
1.5
M
V (V)
1.4
1.3
1.2
1.1
1
0.9
0.8
10
0
10
W /W
p
n
1
Inverter
Determining VIH and VIL
A simplified approach
Vout
V OH
VM
V in
V OL
V IL
V IH
Inverter
Simulated VTC
2.5
2
Vout(V)
1.5
1
0.5
0
0
0.5
1
1.5
2
2.5
V (V)
in
Inverter
Inverter Gain
0
-2
-4
gain
-6
-8
-10
-12
-14
-16
-18
0
0.5
1
1.5
2
2.5
V (V)
in
Inverter
Gain as a function of VDD
2.5
0.2
2
0.15
Vout(V)
Vout (V)
1.5
0.1
1
0.05
0.5
Gain=-1
0
0
0.5
1.5
1
V (V)
in
2
2.5
0
0
0.05
0.1
V (V)
0.15
0.2
in
Inverter
Impact of Process Variations
2.5
2
Wider PMOS
Good PMOS
Bad NMOS
Nominal
Vout(V)
1.5
1
Wider NMOS
Good NMOS
Bad PMOS
0.5
0
0
0.5
1
1.5
2
2.5
Vin (V)
Inverter
Inverter
Inverter
Inverter
Inverter
Inverter
Inverter
Inverter
Inverter
t/τ
Inverter
Inverter
The Book’s Method
Page 76
Inverter
Inverter
Inverter
导线电容
Inverter
Inverter
Lumping the Caps
Inverter
Inverter
Inverter
Inverter
再生性
Inverter
Propagation Delay
Inverter
Transient Response
3
2.5
Vout(V)
电平
?
2
tp = 0.69 CL (Reqn+Reqp)/2
1.5
1
S->D的电容有跳变
tpHL
tpLH
0.5
0
-0.5
0
0.5
1
1.5
t (sec)
2
2.5
-10
x 10
Inverter
Inverter
Inverter
时延增加
Inverter
Inverter
Inverter
Power Dissipation
Inverter
Where Does Power Go in CMOS?
Inverter
Dynamic Power Dissipation
Inverter
Dynamic Power Dissipation
Inverter
Inverter
Short Circuit Currents
Inverter
Diode Leakage
GATE
p+
p+
N
Reverse Leakage Current
+
V
- dd
IDL = JS  A
JS = 10-100 pA/m2
at 25 deg C for 0.25m CMOS
JS = 1-5pA/m2 for a 1.2m CMOS technology
JS doubles for everyo 9 deg C!
Js double with every 9 C increase in temperature
Much
smaller than transistor leakage
Inverter
Inverter
Inverter
Inverter
Inverter
Inverter
Inverter
Principles for Power Reduction
 Prime
choice: Reduce voltage!
 Recent years have seen an acceleration in
supply voltage reduction
 Design at very low voltages still open
question (0.6 … 0.9 V by 2010!)
 Reduce
switching activity
 Reduce physical capacitance
 Device Sizing: for F=20
– fopt(energy)=3.53, fopt(performance)=4.47
Inverter
Inverter
Inverter
Inverter
Inverter
Inverter
Inverter
Inverter
Inverter
Inverter
Inverter
Inverter
Inverter
Inverter
Inverter
Inverter
Inverter
Inverter