Download Power Issues in Embedded Systems

Outline
The Big Picture
Who’s got the Power?
What’s in the bag of tricks?
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The Big Picture
Phenomenal increase in processor
speed
3GHz Pentium 4 by the end of the year
Shrinkage in size
Mobility highly desired
BUT battery technology not improving at
the same rate
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Batteries Not Included
Nickel-based batteries
Nickel-Iron
The first rechargeable, old technology
Nickel-cadmium and Nickel-Metal-Hydride
High energy density – good for motors
Lithium-based batteries
Promising because lithium releases electrons
easily
Problem with battery life, dangerous to handle
Others
Zinc-air batteries – can work a laptop for 10 hours
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Some Terminologies
Power is the rate of energy consumption
Power ≠ energy
Energy depends on how long you run the thing!
Optimizing for speed = optimizing for energy?
Some researchers look at average power
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Back to Basics
Gate oxide insulator
Gate
N+
source
 



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
P-


substrate
N+ drain


N-Channel Metallic Oxide Semiconductor Field
Effect Transistor

6
Back to Basics – ACTION!

Gate oxide insulator
-
Gate

+

N+ source
 

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+





P-
N+ drain


substrate



N-Channel Metallic Oxide Semiconductor Field
Effect Transistor
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CMOS
VDD
P-channel MOSFET
Input:
0 = 0V
1 = +5V
Output
CMOS Inverter
N-channel MOSFET
GND
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CMOS
VDD
P-channel MOSFET
Input:
0 = 0V
Output = 0
CMOS Inverter
N-channel MOSFET
GND
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CMOS
VDD
P-channel MOSFET
Input:
1 = +5V
Output = 1
CMOS Inverter
N-channel MOSFET
GND
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Power in CMOS
1
2
P   C  VDD
 f  N  QSC  VDD  f  N  I leak  VDD  I static  VDD
2
P = total power
VDD = supply voltage
f = clock frequency
N = switching (gate transition per clock cycle)
Ileak = leakage power
Istatic = static power
QSC = quantity of charge carried by short-circuit current per
transistion
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Power in CMOS
1
2
P   C  VDD
 f  N  QSC  VDD  f  N  I leak  VDD  I static  VDD
2
Switching power
Short-circuit power
Dynamic power
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Embedded Seminar
Leakage
power
Static
power
Static power
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Switching Power
Accounts for most (90%) of power
Two major factor is supply voltage and
frequency
Voltage scaling
Frequency scaling
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Short Circuit Power
During switching, there is a short period
of time when both gates are ON
 a path from VDD to ground
 power dissipation
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Leakage Power
Diode leakage
Source (and drain) together with substrate
forms a diode
At times, this diode can be reverse-biased
during which current can leak
Sub-threshold leakage
Even when gate is not completely on,
enough of a channel can form for some
movement of charges from source to drain
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Static Power
Reduced voltage feeding
Both gates can be “weakly on”
Weak current flow from VDD to ground
Other parasitic current flows
Due to imperfect manufacturing or
operating conditions
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A Digression – The Problems Of
Scaling down
Latch-up effect
Short-channel effect
Punch-through effect
Hot electron effect
Gate erosion
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Latch-up Effect
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Tricks in the bag
Voltage Scaling
Frequency Scaling
Power Gating
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Voltage Scaling
Lower VDD
For the same circuit and technology, this
leads to higher gate delay
Total delay, , is made up of two
components,  = 1 + 2
1 is a constant
2  VDD
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Frequency Scaling
Widely used in many processors
Intel SpeedStep on mobile processors
Leads to lower performance
Obvious!
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Power Gating
Turn off power to parts of the circuit
Can be problematic for circuits with
memory
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What About Memory?
SRAM
Implemented using CMOS
DRAM
Entirely different technology
Implemented using capacitors
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SRAM
CMOS SRAM Cell
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DRAM
Single Transistor DRAM cell
Model or Measure?
Hardware measurement
Measures the amount of current
consumed
Depends on how the circuit is designed
Cannot get core CPU power breakdowns
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Software Estimation
SPICE simulation
Very slow
PowerMill from Synopsys
CAD Tools
Part of a lot of CAD tool chains, eg.
Synopsys
Architectural based simulation
Eg: SimplePower, WATTCH etc.
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Putting it Together –
System Power
Reference:
Marc A. Viredaz and Deborah A. Wallach,
“Power Evaluation of a Handheld
Computer: A Case Study”. Compaq
Western Research Lab Technical Report
2001/1. May 2001.
http://research.compaq.com/wrl/techreports/abstracts/2001.1.html
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Dealing with it
System / OS
Algorithms
Architecture
Circuit/Logic
Technology
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Technology
Low threshold, low voltage
Various technological issues as
discussed
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Circuit/Logic
Even within CMOS, there are different
types of logic families that consumes
different amount of energy
Transistor size
Layout
Asynchronous circuits
Clocking consumes a lot of power
Pipeline retiming
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Architecture / Compiler
Trade off area for power
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Architecture / Compiler
Trade off area for power
Shorter wires less power
Parallelism and concurrency
Directives to allow compiler to do
Voltage scaling
Frequency scaling
Power gating
One more degree of freedom: activity
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Algorithms
Low power algorithms
Parallelism and concurrency
A under-research area
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System / OS
System level power management
Heuristics for transiting between various
power modes
Operating environment sensitive power
management
Battery or plugged-in?
Power-domain specific management
schemes
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Reducing Processor Power
Energy conscious code generation
Reduce switching
Instruction scheduling
Use of Gray code instead of binary
Low power modes
Instruction compression
Parallelism and concurrency
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Reducing Memory Power
Reduce memory accesses
All compiler techniques for reducing cache
misses
Use registers
Memory reference compaction
Power aware page allocation
Group active pages together
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Reducing Peripheral Power
Communication
Different power modes for communicating
devices
Data compression
Adaptation in view of traffic and power
Disk
Spin-down and different power modes
(when?)
Display
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Summary
Some research opportunities still exist
Especially in algorithms and operating
systems
An integrated approach is needed
All levels of the system cooperating with
one another
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