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Valeriy Shunkov, Pavel Osipenko, Eduard Atkin
Scientific Research Institute for System Analysis, Moscow Engineering Physics Institute
Radiation Hardened Design
for STS on SOI technology
12th CBM collaboration meeting, Dubna, 13th-16th of October, 2008
SRISA research fab
•Scientific Research Institute for System
Analysis has its own research
semiconductor fab.
•This fab produces small amounts of chips
on 0.5 μm 1P3M SOI technology.
•0.35 μm 2P4M technology with analog
options expected in 2009
•0.35 μm technology can be used to design
radhard mixed-signal ICs required for CBM.
•Great MEPhI experience in radhard design
makes SRISA-MEPhI research group to be
perspective partner for CBM collaboration.
12th CBM collaboration meeting, Dubna, 13th-16th of October, 2008
Main advantages of SOI
The main advantages of SOI technology for
radiation hardened design are following:
1) Lower SEE sensitivity
2) Better performance
3) Simpler design
In SOI chip area and power can be strongly
reduced because there is no need to use enclosed
gate transistors.
Body-tied strip transistors used to suppress intratransistor leakages for better dose performance
and to suppress parasitic bipolar effect for better
SEE performance.
The 0.35 μm SOI can provide same or better
performance than 0.18 μm bulk.
12th CBM collaboration meeting, Dubna, 13th-16th of October, 2008
Total dose test results
Total dose tests of 0.5 μm SOI technology indicated that single
transistors remains working up to 8 Mrad.
Test circuits based on standard design with body-tied transistors
showed parametric failures just above 2 Mrad.
There wasn’t any sufficient influence of total dose on SEE
performance of test circuits.
The first tests of 0.35 μm have shown threshold shift about 0.1 V
1,1
Threshold voltage, V
1,0E-03
Leakage current, А
1,0E-04
1,0E-05
1,0E-06
1,0E-07
1,0E-08
1,0E-09
1,0E-10
1,0E-11
1
0,9
0,8
0,7
0,6
0,5
0,4
1,0E-12
0
2000
4000
Total Dose, krad
6000
8000
0
800
1600 2400 3200 4000 4800 5600 6400 7200 8000 8800 9600
Dose
12th CBM collaboration meeting, Dubna, 13th-16th of October, 2008
SEU test results
Two SRAM test chips with 8 types of memory cells
were designed and tested on SEU with Cf-262 source
(provides LET up to 20 MeV·cm2/mg).
Designed standard SRAM had saturated cross-section
10-7 cm2/bit and threshold LET 7 MeV·cm2/mg.
Designed hardened SRAMs demonstrated no upsets
at LET 20 MeV·cm2/mg.
Our design increases cell area only on 30% instead
of double increasing typical to DICE cell.
Typical 0.18 μm SRAMs have saturated cross-section
about 10-7-10-8 cm2/bit and threshold LET about 1-3
MeV·cm2/mg.
0.35 μm SOI hardened SRAM cell has similar area
and power consumption with 0.18 μm DICE cell.
12th CBM collaboration meeting, Dubna, 13th-16th of October, 2008
Approaches for CBM readout
electronics
SRISA and MEPhI have a large experience in radiation hardened
design.
0.35 µm 2P4M SOI technology is suitable for designing digital and
mixed-signal chips with very high radiation hardness.
SOI design is simpler than bulk design and can provide very high
robustness.
0.35 µm SOI technology provides the same performance as 0.18
µm bulk technology with special radiation hardened design.
This means that SRISA and MEPhI cooperation in the field of SOI
could be effectively used in CBM experiment. It might be a good
back-up solution for STS readout electronics.
12th CBM collaboration meeting, Dubna, 13th-16th of October, 2008