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Transcript
Activities so far Meeting at Imperial, Paul and Matt A part of work on preparation for testing of the ASIC1 reallocated from Matt to me: o Readout PCB o (tbc) a part of firmware for the control board Vladimir Rajović / Birmingham MAPS, RAL, 7-Mar-2007 Readout PCB 100 – 160 mm There are mechanical constraints, seemed not too harsh at first glance Sensor Edge clearance 2mm Readout PCB 70 – 150 mm Vladimir Rajović / Birmingham MAPS, RAL, 7-Mar-2007 Readout PCB Test Bump Pads Test Structures Pad & Power Ring Control Pixels 64x64 64x64 Still not known: • most important: pin out of ASIC1? 64x64 Readout • how many I/O? • how many variable voltage references; what precision? 64x64 For the above, an input from RAL is awaited • clock, control & readout connector(s)? (to be settled down through contact with Imperial) Vladimir Rajović / Birmingham MAPS, RAL, 7-Mar-2007 Readout PCB Preliminary working assumptions: • 40 input + 40 output MAX • 20 analog voltage references MAX, precision not really known, working out multiple possibilities while waiting • linear power supplies, in order to avoid noise off switching power supplies Now it does not seem that relaxed regarding mechanical constraints, quite a lot of external components might be needed Not a problem packing them within given constraints – personally would prefer more space for relaxed physical separation of LVDS, analog and digital sections of the board Vladimir Rajović / Birmingham MAPS, RAL, 7-Mar-2007 Control Board firmware There is a plan that a daughter board holding 1Mx18 bit SRAM for buffering of readout data is attached to the control board The SRAM interface firmware block is not written yet, not 100% sure whether Matt or I will write it (not really on agenda at the moment) Vladimir Rajović / Birmingham MAPS, RAL, 7-Mar-2007