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A Novel 2.4 GHz CMOS Class-E Power Amplifier with
Efficient Power Control for Wireless Communications
R. Meshkin, A. Saberkari*, and M. Niaboli
Department of Electrical Engineering
University of Guilan
Rasht, Iran
International Conference on Electronics, Circuits and Systems
Athens, Greece
Dec. 2010
Outline
• Introduction
• Baseline Class-E Power Amplifier Topology
• Expressions and Relationships
• Conventional Power Control Techniques
• Design Procedure
• Circuit Characterization
• Conclusion
Introduction Baseline Top. Expressions
Conv. Power
Design Proc.
Characterize
Conclusion
2
Introduction
• Power Amplifier (PA)
 The Last Building Block of a Transmitter Chain in Transceiver ICs
 The Most Power Consuming Block in any RF Transmitter
 Linear and Nonlinear PAs
• Linearity is in conflict with Efficiency.
•Constant Envelope Modulation Scheme => Nonlinear PAs
• Class-E PA => Better Choice in Terms of
 Circuit Simplicity
 High Efficiency
 Good Performance at Higher Frequencies
Introduction Baseline Top. Expressions
Conv. Power
Design Proc.
Characterize
Conclusion
Conclusion
3
Baseline Class-E PA Topology
Soft Switching Properties:
V DS
tON
dV DS
dt
0
tON
0
Classical Class-E Power Amplifier Topology
Introduction Baseline Top. Expressions
Conv. Power
Design Proc.
Characterize
Conclusion
4
Expressions and Relationships
Load Network Components Value:
L  0.732
R opt
Ropt = Optimum Load Resistance

Pout = Desired Output Power
1
C P  0.685
 R opt
R opt
ω = Resonant Frequency
V dd 2
 1.365
Pout
Vdd = Supply Voltage
Efficiency:
DE 
Pdc = Supply Power
Pout
Pdc
PAE 
Pout = Output Power
Pout  Pin
Pdc
Introduction Baseline Top. Expressions
Pin = Input Power
Conv. Power
Design Proc.
Characterize
Conclusion
5
Conventional Power Control Techniques
• Power
Control with Variable Supply Voltage
Introduction
Introduction Baseline Top. Expressions
Conv. Power
Design Proc.
Characterize
Conclusion
6
Conventional Power Control Techniques
• Power Control with Parallel Amplification
Introduction
Introduction Baseline Top. Expressions
Conv. Power
Design Proc.
Characterize
Conclusion
7
Conventional Power Control Techniques
• Power Control with Array of Switches with Different Sizes
Introduction
Introduction Baseline Top. Expressions
Conv. Power
Design Proc.
Characterize
Conclusion
8
Design Procedure
• Two-Stage Configuration (Driver Stage and Power Stage)
• Cascode Transistor:
 High Isolation from the Input to the Output
 Protect Switching Transistors (Breakdown)
• Class-E Driver Stage => More Efficiency & Closer to Optimum Driving Signal
• Matching Network => As Much as Possible Power from Source to the Load
Proposed Class-E Power Amplifier
Introduction
Introduction Baseline Top. Expressions
Conv. Power
Design Proc.
Characterize
Conclusion
9
Design Procedure
• Output Power Control:
 Changing the Size of the Switching Devices, And
 Suitable External Shunt Capacitors Calculated for Each Steps of Output Power
• Small Size Controlling Switches => located in the Gate Terminal due to the Low Current
of Gate
Proposed Structure for Output Power Control
Introduction
Introduction Baseline Top. Expressions Conv. Power Design Proc. Characterize
Conclusion
10
Design Procedure
Circuit Elements Value
M1,M2
270m
0.18m
Lf
0.71 nH
M3,M4
2430  m
0.18 m
L1
1.39 nH
M3΄,M4΄
1320  m
0.18 m
L2
1.1 nH
M3΄΄,M4΄΄
1110  m
0.18 m
RL
50 Ω
M3΄΄΄,M4΄΄΄
Vbias1
0.2 V
M3΄΄΄΄,M4΄΄΄΄
990  m
0.18 m
930  m
0.18 m
Vbias2
0.65 V
Cm1
2.3 pF
Vdd
1.8 V
Lm1
1.55 nH
CP
52 fF
Cm2
10 pF
CP΄
890 fF
Lm2
0.6 nH
CP΄΄
953 fF
Cm3
2.8 pF
CP΄΄΄
990 fF
Lm3
1.28 nH
CP΄΄΄΄
1 pF
Cf
5 pF
Introduction
Introduction Baseline Top. Expressions
Conv. Power
Design Proc.
Characterize
Conclusion
11
Design Procedure
Chip Layout
1381 µm*1234 µm
Introduction
Introduction Baseline Top. Expressions
Conv. Power
Design Proc.
Characterize
Conclusion
12
Circuit Characterization
Drain Current and Voltage Waveforms of Cascode Transistor M4
Introduction
Introduction Baseline Top. Expressions
Conv. Power
Design Proc.
Characterize
Conclusion
13
Circuit Characterization
Output Power and PAE Versus Supply Voltage
Introduction
Introduction Baseline Top. Expressions
Conv. Power
Design Proc.
Characterize
Conclusion
14
Circuit Characterization
Output Power and PAE as a Function of Frequency
Introduction
Introduction Baseline Top. Expressions
Conv. Power
Design Proc.
Characterize
Conclusion
15
Circuit Characterization
Output spectrum
Introduction
Introduction Baseline Top. Expressions
Conv. Power
Design Proc.
Characterize
Conclusion
16
Circuit Characterization
PAE Values for Each Output Power Step
Control
Word
Output Power
(dBm)
PAE
(%)
10000
21.09
57
01000
20
47.5
00100
19
41
00010
18
36
00001
17
33
Introduction
Introduction Baseline Top. Expressions
Conv. Power
Design Proc.
Characterize
Conclusion
17
Circuit Characterization
Performances in Comparison with Previous Works
References
Technology
(µm)
Frequency
(GHz)
Supply
(V)
Output
Power
(dBm)
PAE
(%)
[1]
CMOS 0.25
2.4
2.5
24
48
[2]
CMOS 0.13
1.7
2.5
31
58
[3]
CMOS 0.13
2.4
7
25.8
38.8
[4]
CMOS 0.18
2.4
3.3
19.2
27.8
This work
CMOS 0.18
2.4
1.8
21.09
57
[1] V. R. Vathulya, T. Sowlati and D. Leenaerts, 2001.
[2] R. Brama, L. Larcher, A. Mazzanti and F. Svelto, 2007.
[3] H. Fouad, A.H. Zekry and K. Fawzy, 2009.
[4] S.A.Z, Murad, R.K. Pokharel, H. Kanaya and K. Yoshida, 2010.
Introduction
Introduction Baseline Top. Expressions
Conv. Power
Design Proc.
Characterize
Conclusion
18
Circuit Characterization
Comparison of PAE Drop in Different Output power Control Method
References
Control Method
Drop (%)
[1]
Parallel Amplification
22%
[2]
Change Driver Stage Size
15%
[3]
Bias Regulation
10%
This work
Proposed Technique
14.5%
[1] A. Sirvani, D. K. Su, B. A. Wooley, 2002.
[2] M. M. Hella and M. Ismail, 2002.
[3] C. Wei, L.Wei and H. Shizhen, 2009.
Introduction
Introduction Baseline Top. Expressions
Conv. Power
Design Proc.
Characterize
Conclusion
19
Conclusion
• Reviewed Concepts of Classical Class-E Power
Amplifiers
• Presented Topological Modifications that Improve
PAE and Circuit Integration Capability
• Presented New Efficiently Output Power Control
Technique Based on the Array of Switches and
Capacitors
Introduction
Introduction Baseline Top. Expressions
Conv. Power
Design Proc.
Characterize
Conclusion
20