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Green Transistor for 10X Lower IC Power ?
Chenming Hu
University of California, Berkeley
Supported by: DARPA STEEP, FCRP-MSD
Electronics Infrastructure
the world enabled
electronic systems
IC chips
$
fabs
transistors
27nm
30nm
Buried Oxide
6/2009 Chenming Hu
Expectation:
ICs will be even more..
• Affordable (size reduction..):
manufacturing, device physics limit,…
• Useful (speed, density..): natural human
interface, bio-medical sensing…
• Usable (low power): heat management,
portability, global energy conservation…
6/2009 Chenming Hu
Power Consumption Problems
1. Thermal management/package issues may
limit integration density.
2. IC usage of electricity at an inflection point.
• ICs use a few % of world’s electricity today and
growing exponentially.
• Power per chip is growing.
• IC units in use also growing.
3. Need to reduce IC power consumption with
architecture and circuit innovations, and a
low voltage transistor.
6/2009 Chenming Hu
IC Power Consumption Rising Much Faster Than
Past Trend
• Because power consumption Vdd2
• and Vdd (operation voltage) scaling has
slowed.
Technology
Node
Vdd
0.25
μm
0.18
μm
0.13
μm
90
nm
65
nm
45
nm
32
nm
22
nm
16
nm
2.5 V 1.8 V 1.3 V 1.2 V 1.1 V 1.0 V 0.9 V 0.8 V 0.7 V
High Performance ITRS Roadmap
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Why Vdd scaling slowed
•We used to control power by scaling Vdd and
maintain good speed by reducing Tox.
Speed transistor current μ ( Vdd – Vt ) / Tox
•But, Tox can not be reduced much more, not
even with high-k dielectrics.
•But new materials will raise the mobility, μ
1.2 nm SiO2
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New material, e.g. Ge film on Si substrate
Gate
3nm Ge film
Source
Drain
Oxide
Silicon
Industry is also funding InGaAs, InAs, and
graphene MOSFET research.
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How to Reduce Power by 20X
Two steps to reduce Vdd to 0.2V for 20x power
reduction?
1. Reduce Vdd – Vt to < 0.15V with highmobility-channel material (Ge, III-V,
graphene...), etc.
2. Reduce Vt to 50mV. But, there is the
fundamental 60mV/decade turn-off limit …..
6/2009 Chenming Hu
Ioff Limit - 60mV/decade Swing
Drain Current, IDS (A/m m)
Lowering Vt by 60mV increases the leakage
current (power) by 10 times.
-3
10
Source: Intel Corporation
Lower
V
Vt t
-5
10
-7
10
I d (Vg  0)  I d (Vg  Vt )e
-9
10

Vt
Vs
-11
10
0.0
0.3
0.6
0.9
Gate Voltage, VGS (V)
9
6/2009 Chenming Hu
The “fundamental” 60mV/decade Limit
VG
COX
Ec
Ev
Source
Channel
Drain
Electrons go over a potential barrier. Leakage current is
determined by the Boltzmann distribution or 60
mV/decade, limiting MOSFET, bipolar, graphene
MOSFET…
How to overcome the limit:
Let electrons go through the energy barrier,
not over it  tunneling
10
6/2009 Chenming Hu
Semiconductor Band-to-Band Tunneling
EC
EV
A known mechanism of leakage current since 1985.
J. Chen, P. Ko, C. Hu, IEDM 1985
Called Gate Induce Drain Leakage (GIDL) because
the current depends on the gate voltage.
6/2009 Chenming Hu
Basic Tunnel Transistor Structure
N+ Source
P-
P+ Drain
Some references
W. Reddick, G. Amaratunga, Appl. Phys. Letters, vol. 67, 1994.
W. M. Reddick, et al., Appl. Phys. Lett., vol. 67(4), pp. 494-497, 1995.
C. Aydin, A. Zaslavsky, et al., Appl. Phys. Lett., vol. 84(10), pp. 1780-82, 2004.
WY. Choi et al., Tech. Dig. Int. Electron Device Meet, pp. 955-958, 2005.
K. K Bhuwalka, et al., Jpn. J. of Appl. Phys., vol. 45(4B), pp. 3106-3109, 2006.
Th. Nirschl, et al., Electron Device Letters, vol. 28(4), p. 315, 2007.
~100X less current than MOSFET
Need a more optimal tunneling transistor structure.
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Green Transistor (gFET)--Simulation
G
P+ Pocket
S
N+
P-
P+
C. Hu et al, 2008 VLSI-TSA, p.14, April, 2008
D
Buried Oxide
P+ Pocket
Gate
Hole flow
Electron flow
Energy band diagram
N+ Source
P+ Drain
Simulated carrier generation rates
Large field, good capacitive coupling between gate and pocket,
abrupt turn-on due to over-lap of valence/conduction bands,
adjustable tun-on voltage.
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gFET vs Basic Tunnel FET-simulation
1E-03
EOT= 1 nm
VDD=1V
Lg=40nm
Drain Current,
DS (A/µm)
I DSI(A/um)
1E-04
1E-05
1E-06
EOT= 4.5 nm
VDD=4V
gFET
1E-07
1E-08
1E-09
1E-10
1E-11
Basic Tunnel
FET *
-4.0 -3.5 -3.0 -2.5 -2.0 -1.5 -1.0 -0.5
0.0
Gate Voltage, VVGSGS (V)
(V)
C. Hu et al, 2008 VLSI-TSA, p.14, April, 2008
* K. K Bhuwalka, et al., Jpn. J. of Appl. Phys.,
vol. 45(4B), pp. 3106-3109, 2006
6/2009 Chenming Hu
Drain Current,
IDS (µA/µm)
Ids (uA/um)
Simulated Id-Vd of 0.5V Ge gFET
800
Vgs: 0.5 V
700
Vgs: 0.4 V
600
Vgs: 0.3 V
EOT=0.5nm
500
400
300
200
100
0
0.0
0.1
0.2
0.3
0.4
0.5
(V)
Drain-Source Vgs
Voltage,
VDS (V)
• Good
output resistance and DIBL.
Lg = 40nm
C. Hu et al, 2008 VLSI-TSA, p.14, April, 2008
6/2009 Chenming Hu
Vdd (Power) Scaling Path: Reduce Band Gap
1E-02
Drain Current, IDS (µ/µm)
1E-03
Eg=0.36eV, Vdd=0.2V, EOT=5 Å, CV/I=0.42pS
1E-04
1E-05
1E-06
Eg=0.69eV, Vdd=0.5V, EOT=7 Å, CV/I=2.2pS
1E-07
Eg=1.1eV, Vdd=1V, EOT=10 Å, CV/I=4.2pS
Ids1E-08
(A/um)
Eg=0.36eV (InAs)
Eg=0.69eV (Ge)
Lg=40nm
Silicon
1E-09
1E-10
1E-11
0.0
0.2
0.4
0.6
0.8
1.0
Gate Voltage, VGS (V)
C. Hu et al, 2008 VLSI-TSA, p.14, April, 2008
6/2009 Chenming Hu
Hetero-tunneling gFET
• In lieu of low Eg semiconductor, a heterojunction
can provide a very small effective tunneling band
gap, Egeff.
Gate
~
N+ Drain
A
B Substrate
Gate Oxide
P+ Source
~
Gate
~
Egeff EC
EV
~
A
B
Egeff is 0.3eV for Si/Ge hetero-tunneling gFET.
A. Bownder et al., 8th International workshop Junction
Technology, Extended Abstracts , p.93, 2008. Also
IEEE Silicon Nanoelectronics Workshop, 2008.
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Compound Semiconductors
Egeff
• Wide choices of heterojunction
materials, band engineering and
strain engineering.
•Example: InAs-AlGaSb
provides tunable Egeff from
positive to negative values.
• Very low voltage gFET may be
possible.
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Ge-Source Tunnel Transistor
Gate
P+ Ge
Si
SiO2
1.E-07
Drain
N+ Si
ID [A/mm]
Source
1.E-09
1.E-11
Experiment
1.E-13
Model
1.E-15
-0.6
-0.4
-0.2
0
0.2
0.4
VGS [V]
VD=0.5V
LG=5mm
S [mV/dec]
W=0.33mm
I D  AEs exp(  B / Es )
Es = |VGS+Vtunnel|/(Tox
Vtunnel ~ 0.6V
S. Kim et al., VLSI Tech Symp., 2009
ID [A/mm]
ege/eox)
Green’s Function Based Simulation
Sayeef Salahudin
Summary
• ICs use of world’s electricity is several %
and growing fast.
• A low voltage transistor can slow the
growth.
• Green Transistor may potentially provide
orders-of-magnitude IC power reduction.
6/2009 Chenming Hu