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Transcript
Power Optimization in VLSI Design : Tunable Level Shifter Abu Baker 1 Outline Objective and Background CMOS Power Dissipation CMOS Device Characteristics CMOS Current Mirror Design of Level Shifter Circuit Simulation Delay and Power Analysis Leakage Analysis Comparison Analysis Summary and Discussion 2 Outline Objective and Background CMOS Power Dissipation CMOS Device Characteristics CMOS Current Mirror Design of Level Shifter Circuit Simulation Delay and Power Analysis Leakage Analysis Comparison Analysis Summary 3 NTRS Technology trends: 200-300M chips by 2010 (0.07 micron CMOS) 4 Energy/Power Gap Power ( K Watts) 100 P6 Pentium ® proc 10 8086 286 1 8008 4004 486 Dynamic Growth 386 8085 8080 0.1 1971 1974 1978 1985 Year 1992 2000 Lead Microprocessors power continues to increase Exponential growth in the # of devices per chip + Operating frequencies = Dynamic Growth 5 Design Objectives Challenges VLSI Technology Power Optimization (i.e. Management) Low power Portable Devices 6 Outline Objective and Background CMOS Power Dissipation CMOS Device Characteristics CMOS Current Mirror Design of Level Shifter Circuit Simulation Delay and Power Analysis Leakage Analysis Comparison Analysis Summary and Discussion 7 CMOS Power Consumption 8 Dual Supply Voltage 9 Outline Objective and Background CMOS Power Dissipation CMOS Device Characteristics CMOS Current Mirror Design of Level Shifter Circuit Simulation Delay and Power Analysis Leakage Analysis Comparison Analysis Summary and Discussion 10 CMOS Device Characteristics Small Signal Model Bode Plot 11 Bandwidth Properties Small Signal Model Bode Plot Unity Gain Frequency 12 Outline Objective and Background of the Presentation CMOS Power Dissipation CMOS Device Characteristics CMOS Current Mirror Design of Level Shifter Circuit Simulation Delay and Power Analysis Leakage Analysis Comparison Analysis Summary and Discussion 13 CMOS Current Mirror CMOS Current Mirror Circuit I-V Characteristic of the Active Load Q 2 Graphical Construction to Determine the Transfer Characteristic Transfer Characteristic 14 Outline Objective and Background CMOS Power Dissipation CMOS Device Characteristics CMOS Current Mirror Design of Level Shifter Circuit Simulation Delay and Power Analysis Leakage Analysis Comparison Analysis Summary and Discussion 15 Circuit Schematic for the Level Shifter Vref Out Vin 16 The schematic for the non-stacked output of the buffer for better rise and fall time Vref Out Vin 17 Biasing Circuit 18 Outline Objective and Background CMOS Power Dissipation CMOS Device Characteristics CMOS Current Mirror Design of Level Shifter Circuit Simulation Delay and Power Analysis Leakage Analysis Comparison Analysis Summary and Discussion 19 Simulation Simulation for at 250 MHz from 0.65v to 1.2v Simulation for at 1 GHz from 0.65v to 1.2v spectre The simulation was done with the cadence for the 130nm process for the level shifting from 0.65v and 0.85v to the 1.2v. The duty cycle was set at 37.5 in order to simulate the random data type that the buffer may be used in real application. 20 Outline Objective and Background CMOS Power Dissipation CMOS Device Characteristics CMOS Current Mirror Design of Level Shifter Circuit Simulation Delay and Power Analysis Leakage Analysis Comparison Analysis Summary and Discussion 21 Delay and Power Analysis Non-stacked transistor data at 250 MHz Power (W) 53.23 Fall time (ps) 38.31 56.88 66.83 8.33u Vin Rise time (ps) 0.85 0.65 14.09u Non-stacked transistor data at 1 GHz 0.85 Rise (ps) 88.4 0.65 56.88 Vin time Fall time (ps) 73.46 66.83 Power (W) 8.989u 9.75u 22 Delay and Power Analysis Stacked transistor data at 250 MHz Vin 0.85 0.65 Rise time (ps) 116.6 83.17 Fall time (ps) 85.9 79.9 Power (W) 6.847u 7.96u Stacked transistor data at 1 GHz Vin Rise time (ps) 0.85 116.6 Fall (ps) 87.75 0.65 82.77 81.6 time Power (W) 7.98u 9.3u 23 Outline Objective and Background of the Presentation CMOS Power Dissipation CMOS Device Characteristics CMOS Current Mirror Design of Level Shifter through Mirror Circuit Circuit Simulation Delay and Power Analysis Leakage Analysis Comparison Analysis Summary and Discussion 24 Leakage Analysis Buffer off (Using PMOS switch) Vinput Clk swing 0.85v Constant 0.85v Constant 0 v Pwr Dissipation (W) 1.09u 1.05u 1.049u Buffer off (Using NMOS switch) Vinput Clk swing 0.85v Constant 0.85v Constant 0 v Pwr Dissipation (W) 470n 459n 315n 25 Outline Objective and Background of the Presentation CMOS Power Dissipation CMOS Device Characteristics CMOS Current Mirror Design of Level Shifter through Mirror Circuit Circuit Simulation Delay and Power Analysis Leakage Analysis Comparison Analysis Summary and Discussion 26 Comparison Analysis Different Type of LC # of Tr. Delay (ps) Power (uW) PDP (fJ) CSSA 30 510 21.7 11.1 26 1004 11.3 11.3 32 380 11.8 4.5 27 12-14 312 137-245 9.45 14.09-6.847 2.93 1.93-1.7 (Clock-level Shifted SenseAmplifying) SLLS (Slave-Latch Level-Shifting) SPFF (Self-Precharging FF) DE_LCFF CMLC - M. Hamada, et al., “A top-down low power design technique using clustered voltage scaling with variable supply-voltage scheme,” Custom Integrated Circuits Conf., pp. 495–498, 1998. - H. Mahmoodi-Meimand and K. Roy, "Self-precharging flip-flop (SPFF): A new level converting flipflop," in Proc. European Solid-State Circuits Conference 2002, pp.407--410, Sep. 2002. - Peiyi Zhao, Golconda Pradeep Kumar, Archana C. and Magdy Bayoumi, “A Double-Edge ImplicitPulsed Level Convert Flip-Flop”, Proceedings of the IEEE Computer Society Annual Symposium on VLSI Emerging Trends in VLSI Systems Design (ISVLSI’04). 27 Comparison Analysis Different Type of LC # of Tr. Delay (ps) Power (uW) PDP (fJ) MSCC 26 287 9.13 2.62 33 184 15.56 2.863 23 259 9.03 2.341 23 204 8.84 1.81 31 181 9.72 1.755 27 312 9.45 2.93 12-14 137-245 14.09-6.847 1.93-1.7 (Master-Slave, CrossCoupled) PSA (Pulsed,Sense Amplifierbased) MSHL (Master-Slave, Half-Latch) PHL (Pulsed, Half-Latch) PPR (Pulsed, Precharged LC) DE_LCFF CMLC - Fujio Ishihara, Farhana Sheikh, Borivoje Nikolic, “Level Conversion for Dual –Supply Systems,” IEEE Transactions on VLSI Systems, Vol. 12, No. 2, February 2004. 28 Outline Objective and Background of the Presentation CMOS Power Dissipation CMOS Device Characteristics CMOS Current Mirror Design of Level Shifter through Mirror Circuit Circuit Simulation Delay and Power Analysis Leakage Analysis Comparison Analysis Summary and Discussion 29 Summary and Discussions Gate level power optimization with dual-supply voltages. Dual-voltage approach can achieve significant power saving without degrading timing performance of the circuit. A tunable Thus level shifter has been presented with some power analysis. this analog buffer could be integrated as part of the analog I/O ring as oppose to be part of the digital on chip thus saving on chip space and die size. 30 Thank You 31 Questions 32 Current –Voltage Relationship 33