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Digital Circuits
The Inverter
© Digital Integrated Circuits2nd
Modified From "Digital Integrated
Circuits", by J. Rabaey, A.
Chandrakasan and B. Nikolic. Copyright
1996 UCB
Inverter
Outline







The transistor as a switch
Overview
The Inverter: Basics
Transfer Characteristics
Propagation Delay
Inverter Sizing
Power Consumption
Modified From "Digital Integrated
Circuits", by J. Rabaey, A.
Chandrakasan and B. Nikolic. Copyright
Modified From "Digital Integrated Circuits", by1996
J. Rabaey,
UCB A. Chandrakasan and B. Nikolic
The Transistor as a switch
Modified From "Digital Integrated
Circuits", by J. Rabaey, A.
Chandrakasan and B. Nikolic. Copyright
Modified From "Digital Integrated Circuits", by1996
J. Rabaey,
UCB A. Chandrakasan and B. Nikolic
Switches
Modified From "Digital Integrated
Circuits", by J. Rabaey, A.
Chandrakasan and B. Nikolic. Copyright
Modified From "Digital Integrated Circuits", by1996
J. Rabaey,
UCB A. Chandrakasan and B. Nikolic
Switches
Modified From "Digital Integrated
Circuits", by J. Rabaey, A.
Chandrakasan and B. Nikolic. Copyright
Modified From "Digital Integrated Circuits", by1996
J. Rabaey,
UCB A. Chandrakasan and B. Nikolic
Switches
Modified From "Digital Integrated
Circuits", by J. Rabaey, A.
Chandrakasan and B. Nikolic. Copyright
Modified From "Digital Integrated Circuits", by1996
J. Rabaey,
UCB A. Chandrakasan and B. Nikolic
Overview
Modified From "Digital Integrated
Circuits", by J. Rabaey, A.
Chandrakasan and B. Nikolic. Copyright
Modified From "Digital Integrated Circuits", by1996
J. Rabaey,
UCB A. Chandrakasan and B. Nikolic
The Inverter
V DD
vin
vout
Modified From "Digital Integrated
Circuits", by J. Rabaey, A.
Chandrakasan and B. Nikolic. Copyright
Modified From "Digital Integrated Circuits", by1996
J. Rabaey,
UCB A. Chandrakasan and B. Nikolic
DC Operation
Voltage Transfer Characteristic
V(y)
V
VOH = f(VOL)
VOL = f(VOH)
VM = f(VM)
f
OH
V(y)=V(x)
VM Switching Threshold
V OL
V IL
V
IH
V(x)
Nominal Voltage Levels
Modified From "Digital Integrated
Circuits", by J. Rabaey, A.
Chandrakasan and B. Nikolic. Copyright
Modified From "Digital Integrated Circuits", by1996
J. Rabaey,
UCB A. Chandrakasan and B. Nikolic
Mapping between analog and digital signals
V
“ 1”
V
OH
V
V
IH
out
Slope = -1
OH
Undefined
Region
V
“ 0”
V
Slope = -1
IL
V
OL
OL
V
IL
V
IH
Modified From "Digital Integrated
Circuits", by J. Rabaey, A.
Chandrakasan and B. Nikolic. Copyright
Modified From "Digital Integrated Circuits", by1996
J. Rabaey,
UCB A. Chandrakasan and B. Nikolic
V
in
Definition of Noise Margins
"1"
V
OH
Noise margin high
NM H
V
IH Undefined
Region
V
OL
NM L
V
IL
Noise margin low
"0"
Gate Output
Gate Input
Modified From "Digital Integrated
Circuits", by J. Rabaey, A.
Chandrakasan and B. Nikolic. Copyright
Modified From "Digital Integrated Circuits", by1996
J. Rabaey,
UCB A. Chandrakasan and B. Nikolic
Noise Immunity


Noise margin measures the capability of a circuit to
overpower a noise source
Noise immunity expresses the ability of a system to process
and transmit correctly in the presence of noise:
 Good noise immunity, input-output noise transfer function
is less than 1
Modified From "Digital Integrated
Circuits", by J. Rabaey, A.
Chandrakasan and B. Nikolic. Copyright
Modified From "Digital Integrated Circuits", by1996
J. Rabaey,
UCB A. Chandrakasan and B. Nikolic
Regenerative Property
...
v1
v0
v2
v3
v4
v5
v6
(a) A chain of inverters.
v1, v3, ...
v1, v3, ...
finv(v)
f(v)
finv(v)
v0, v2, ...
f(v)
v0, v2, ...
(b) Regenerative gate Modified From "Digital Integrated
(c) Non-regenerative gate
Circuits", by J. Rabaey, A.
Chandrakasan and B. Nikolic. Copyright
Modified From "Digital Integrated Circuits", by1996
J. Rabaey,
UCB A. Chandrakasan and B. Nikolic
Key Reliability Properties

Absolute noise margin values are deceptive


a floating node is more easily disturbed than a node driven by a low
impedance (in terms of voltage)
Noise immunity is the more important metric – the capability
to suppress noise sources

Key metrics: Noise transfer functions, Output impedance of the driver
and input impedance of the receiver;
Modified From "Digital Integrated
Circuits", by J. Rabaey, A.
Chandrakasan and B. Nikolic. Copyright
Modified From "Digital Integrated Circuits", by1996
J. Rabaey,
UCB A. Chandrakasan and B. Nikolic
Fan-in and Fan-out
N
Fan-out N
M
Fan-in M
Modified From "Digital Integrated
Circuits", by J. Rabaey, A.
Chandrakasan and B. Nikolic. Copyright
Modified From "Digital Integrated Circuits", by1996
J. Rabaey,
UCB A. Chandrakasan and B. Nikolic
The Ideal Gate
V out
Ri = 
Ro = 0
Fanout = 
NMH = NML = VDD/2
g=
V in
Modified From "Digital Integrated
Circuits", by J. Rabaey, A.
Chandrakasan and B. Nikolic. Copyright
Modified From "Digital Integrated Circuits", by1996
J. Rabaey,
UCB A. Chandrakasan and B. Nikolic
Delay Definitions
Vin
50%
t
t
Vout
t
pLH
pHL
90%
50%
10%
tf
t
tr
Modified From "Digital Integrated
Circuits", by J. Rabaey, A.
Chandrakasan and B. Nikolic. Copyright
Modified From "Digital Integrated Circuits", by1996
J. Rabaey,
UCB A. Chandrakasan and B. Nikolic



Delay depends on technology and topology but also on input
and output signals slopes !!!
Fall and rise times apply to individual waveforms. They are
largely defined by the strength of the driving gate and the load
The de facto standard circuit for delay measurement is the
ring oscillator
Modified From "Digital Integrated
Circuits", by J. Rabaey, A.
Chandrakasan and B. Nikolic. Copyright
Modified From "Digital Integrated Circuits", by1996
J. Rabaey,
UCB A. Chandrakasan and B. Nikolic
Ring Oscillator
v1
v0
v0
v2
v1
v3
v4
v5
T=2t N
Modified From "Digital Integrated
p A.
Circuits", by J. Rabaey,
Chandrakasan and B. Nikolic. Copyright
Modified From "Digital Integrated Circuits", by1996
J. Rabaey,
UCB A. Chandrakasan and B. Nikolic
v5
A First-Order RC Network
R
vin
vout
C
tp = ln (2) t = 0.69 RC;
tr = 2.2 RC
Important modelModified
– matches
delay of inverter
From "Digital Integrated
Circuits", by J. Rabaey, A.
Chandrakasan and B. Nikolic. Copyright
Modified From "Digital Integrated Circuits", by1996
J. Rabaey,
UCB A. Chandrakasan and B. Nikolic
The Inverter: Basics
Modified From "Digital Integrated
Circuits", by J. Rabaey, A.
Chandrakasan and B. Nikolic. Copyright
Modified From "Digital Integrated Circuits", by1996
J. Rabaey,
UCB A. Chandrakasan and B. Nikolic
The CMOS Inverter: A First Glance
V DD
V in
V out
CL
Modified From "Digital Integrated
Circuits", by J. Rabaey, A.
Chandrakasan and B. Nikolic. Copyright
Modified From "Digital Integrated Circuits", by1996
J. Rabaey,
UCB A. Chandrakasan and B. Nikolic
CMOS Inverter
N Well
VDD
VDD
PMOS
2l
Contacts
PMOS
In
Out
In
Out
Metal 1
Polysilicon
NMOS
NMOS
GND
Modified From "Digital Integrated
Circuits", by J. Rabaey, A.
Chandrakasan and B. Nikolic. Copyright
Modified From "Digital Integrated Circuits", by1996
J. Rabaey,
UCB A. Chandrakasan and B. Nikolic
CMOS Inverter
First-Order DC Analysis
V DD
V DD
Rp
V out
V out
VOL = 0
VOH = VDD
VM = f(Rn, Rp)
Rn
V in 5 V DD
V 5 0
Modified From
in "Digital Integrated
Circuits", by J. Rabaey, A.
Chandrakasan and B. Nikolic. Copyright
Modified From "Digital Integrated Circuits", by1996
J. Rabaey,
UCB A. Chandrakasan and B. Nikolic
Voltage Transfer Characteristics
IDn
V in = V DD +VGSp
IDn = - IDp
V out = VDD +VDSp
V out
IDp
IDn
IDn
Vin=0
Vin=0
Vin=1.5
Vin=1.5
V DSp
V DSp
VGSp=-1
VGSp=-2.5
Vin = V DD+VGSp
IDn = - IDp
Vout = V DD+VDSp
Modified From "Digital Integrated
Circuits", by J. Rabaey, A.
Chandrakasan and B. Nikolic. Copyright
Modified From "Digital Integrated Circuits", by1996
J. Rabaey,
UCB A. Chandrakasan and B. Nikolic
Vout
CMOS Inverter Load Characteristics
ID n
PMOS
Vin = 0
Vin = 2.5
Vin = 0.5
Vin = 2
Vin = 1
Vin = 1.5
Vin = 1.5
Vin = 1
Vin = 1.5
Vin = 2
NMOS
Vin = 1
Vin = 2.5
Modified From "Digital Integrated
Circuits", by J. Rabaey, A.
Chandrakasan and B. Nikolic. Copyright
Modified From "Digital Integrated Circuits", by1996
J. Rabaey,
UCB A. Chandrakasan and B. Nikolic
Vin = 0.5
Vin = 0
Vout
CMOS Inverter VTC
NMOS off
PMOS res
2.5
Vout
2
NMOS s at
PMOS res
1
1.5
NMOS sat
PMOS sat
0.5
NMOS res
PMOS sat
0.5
1
1.5
2
NMOS res
PMOS off
2.5
V
Modified From "Digital Integrated
in
Circuits", by J. Rabaey, A.
Chandrakasan and B. Nikolic. Copyright
Modified From "Digital Integrated Circuits", by1996
J. Rabaey,
UCB A. Chandrakasan and B. Nikolic
The Switching Threshold

Switching threshold VM is defined as the point where Vin = Vout
Modified From "Digital Integrated
Circuits", by J. Rabaey, A.
Chandrakasan and B. Nikolic. Copyright
Modified From "Digital Integrated Circuits", by1996
J. Rabaey,
UCB A. Chandrakasan and B. Nikolic
Switching Threshold as a function of
Transistor Ratio

Switching threshold VM is defined as the point where Vin = Vout

Wn
Kn
VM  VT
Ln


2
 Kp
Wp
Lp
Vdd  V
M
 VT

2
Yielding VM as a function of transistor geometries, threshold
voltages and Vdd
VM 
 n /  p VTn  (Vdd  VTp )
1  n /  p
Modified From "Digital Integrated
Circuits", by J. Rabaey, A.
Chandrakasan and B. Nikolic. Copyright
Modified From "Digital Integrated Circuits", by1996
J. Rabaey,
UCB A. Chandrakasan and B. Nikolic
Transistor Ratio Setting

Switching threshold VM is defined as the point where Vin = Vout

K n S n Vdd  VM  VT

2
K pS p
VM  VT




2
With VM = Vdd/2 the right hand side equals, in general to 1, so
that
Sn K p

S p Kn

P transistor wider than N for equal margins
Modified From "Digital Integrated
Circuits", by J. Rabaey, A.
Chandrakasan and B. Nikolic. Copyright
Modified From "Digital Integrated Circuits", by1996
J. Rabaey,
UCB A. Chandrakasan and B. Nikolic
Switching Threshold
Modified From "Digital Integrated
Circuits", by J. Rabaey, A.
Chandrakasan and B. Nikolic. Copyright
Modified From "Digital Integrated Circuits", by1996
J. Rabaey,
UCB A. Chandrakasan and B. Nikolic
Switching Threshold as a function of Transistor
Ratio

VM is relatively insensitive to variations in device ratio.


Example: 0.25m (2.4V) process, setting Sn/Sp to 3, 2.5 and 2 yields
VM of 1.22, 1.18, 1.13
Asymmetrical characteristics: lot of sizing to obtain a
significant shift.

Previous example, Sn/Sp=10 is required to go to 1.5V. Further
increases are prohibitive
Modified From "Digital Integrated
Circuits", by J. Rabaey, A.
Chandrakasan and B. Nikolic. Copyright
Modified From "Digital Integrated Circuits", by1996
J. Rabaey,
UCB A. Chandrakasan and B. Nikolic
Noise Margins
Modified From "Digital Integrated
Circuits", by J. Rabaey, A.
Chandrakasan and B. Nikolic. Copyright
Modified From "Digital Integrated Circuits", by1996
J. Rabaey,
UCB A. Chandrakasan and B. Nikolic
Determining VIH and VIL
Vout
V OH
VM
V in
V OL
V IL
V IH
A simplified approach
Modified From "Digital Integrated
Circuits", by J. Rabaey, A.
Chandrakasan and B. Nikolic. Copyright
Modified From "Digital Integrated Circuits", by1996
J. Rabaey,
UCB A. Chandrakasan and B. Nikolic
Inverter Gain
0
1
g m  K (VM  VT )
2
V
V
ro  A  A
ID
K (VM  VT ) 2
-2
-4
gain
-6
-8
-10
g
-12
g m1  g m 2
l1  l2
g
VA
(VM  VT )
-14
-16
-18
0
0.5
1
1.5
V (V)
in
2
2.5
Gain is almost purely specified by
technology parameters, especially l,
and in minor way, by Vdd and the
transistor sizes
Modified From "Digital Integrated
Circuits", by J. Rabaey, A.
Chandrakasan and B. Nikolic. Copyright
Modified From "Digital Integrated Circuits", by1996
J. Rabaey,
UCB A. Chandrakasan and B. Nikolic
Inverter Gain (Short Channel)
0
-2
-4
gain
-6
-8
-10
r
-12
-14
K pVDsatp
K nVDsatn
-16
-18
0
0.5
1
1.5
V (V)
in
2
2.5
Gain is almost purely specified by
technology parameters, especially l,
and in minor way, by Vdd and the
transistor sizes
Modified From "Digital Integrated
Circuits", by J. Rabaey, A.
Chandrakasan and B. Nikolic. Copyright
Modified From "Digital Integrated Circuits", by1996
J. Rabaey,
UCB A. Chandrakasan and B. Nikolic
Gain as a function of VDD
2.5
0.2
2
0.15
Vout(V)
Vout (V)
1.5
0.1
1
0.05
0.5
Gain=-1
0
0
0.5
1.5
1
V (V)
in
2
2.5
0
0
0.05
0.1
V (V)
in
Modified From "Digital Integrated
Circuits", by J. Rabaey, A.
Chandrakasan and B. Nikolic. Copyright
Modified From "Digital Integrated Circuits", by1996
J. Rabaey,
UCB A. Chandrakasan and B. Nikolic
0.15
0.2
Impact of Process Variations
2.5
2
Simulations for
standard worst case
conditions
Good PMOS
Bad NMOS
Vout(V)
1.5
Nominal
1
Good NMOS
Bad PMOS
0.5
0
0
0.5
1
1.5
2
2.5
Vin (V)
Modified From "Digital Integrated
Circuits", by J. Rabaey, A.
Chandrakasan and B. Nikolic. Copyright
Modified From "Digital Integrated Circuits", by1996
J. Rabaey,
UCB A. Chandrakasan and B. Nikolic
Gain as a function of VDD



Reducing power supply reduces power consumption, but it is
detrimental to the delay of the gate
DC characteristics becomes sensitive to variations
Scaling the supply means reducing signal swing. This typically
helps to reduce internal noise, but also makes the circuits more
sensitive to noise sources that do not scale
Modified From "Digital Integrated
Circuits", by J. Rabaey, A.
Chandrakasan and B. Nikolic. Copyright
Modified From "Digital Integrated Circuits", by1996
J. Rabaey,
UCB A. Chandrakasan and B. Nikolic
Transient Analysis
Modified From "Digital Integrated
Circuits", by J. Rabaey, A.
Chandrakasan and B. Nikolic. Copyright
Modified From "Digital Integrated Circuits", by1996
J. Rabaey,
UCB A. Chandrakasan and B. Nikolic
Transient Analysis



One method is to obtain an equivalent resistance for the
transistor while it is switching
The input is assumed to change instantaneously
Result varies slightly depending on the model assumed
 a) Long channel
 b) Short channel
Modified From "Digital Integrated
Circuits", by J. Rabaey, A.
Chandrakasan and B. Nikolic. Copyright
Modified From "Digital Integrated Circuits", by1996
J. Rabaey,
UCB A. Chandrakasan and B. Nikolic
Fall time analysis
Modified From "Digital Integrated
Circuits", by J. Rabaey, A.
Chandrakasan and B. Nikolic. Copyright
Modified From "Digital Integrated Circuits", by1996
J. Rabaey,
UCB A. Chandrakasan and B. Nikolic
Fall time analysis
Modified From "Digital Integrated
Circuits", by J. Rabaey, A.
Chandrakasan and B. Nikolic. Copyright
Modified From "Digital Integrated Circuits", by1996
J. Rabaey,
UCB A. Chandrakasan and B. Nikolic
Fall time analysis
Modified From "Digital Integrated
Circuits", by J. Rabaey, A.
Chandrakasan and B. Nikolic. Copyright
Modified From "Digital Integrated Circuits", by1996
J. Rabaey,
UCB A. Chandrakasan and B. Nikolic
Fall time analysis
Modified From "Digital Integrated
Circuits", by J. Rabaey, A.
Chandrakasan and B. Nikolic. Copyright
Modified From "Digital Integrated Circuits", by1996
J. Rabaey,
UCB A. Chandrakasan and B. Nikolic
Rise time analysis
Modified From "Digital Integrated
Circuits", by J. Rabaey, A.
Chandrakasan and B. Nikolic. Copyright
Modified From "Digital Integrated Circuits", by1996
J. Rabaey,
UCB A. Chandrakasan and B. Nikolic
Gate delay estimation
Modified From "Digital Integrated
Circuits", by J. Rabaey, A.
Chandrakasan and B. Nikolic. Copyright
Modified From "Digital Integrated Circuits", by1996
J. Rabaey,
UCB A. Chandrakasan and B. Nikolic
Circuit delay estimation
Modified From "Digital Integrated
Circuits", by J. Rabaey, A.
Chandrakasan and B. Nikolic. Copyright
Modified From "Digital Integrated Circuits", by1996
J. Rabaey,
UCB A. Chandrakasan and B. Nikolic
Simplifying the problem
Modified From "Digital Integrated
Circuits", by J. Rabaey, A.
Chandrakasan and B. Nikolic. Copyright
Modified From "Digital Integrated Circuits", by1996
J. Rabaey,
UCB A. Chandrakasan and B. Nikolic
Computing Reff
Modified From "Digital Integrated
Circuits", by J. Rabaey, A.
Chandrakasan and B. Nikolic. Copyright
Modified From "Digital Integrated Circuits", by1996
J. Rabaey,
UCB A. Chandrakasan and B. Nikolic
NMOS transistor, logic 0
Modified From "Digital Integrated
Circuits", by J. Rabaey, A.
Chandrakasan and B. Nikolic. Copyright
Modified From "Digital Integrated Circuits", by1996
J. Rabaey,
UCB A. Chandrakasan and B. Nikolic
NMOS transistor, logic 0
Modified From "Digital Integrated
Circuits", by J. Rabaey, A.
Chandrakasan and B. Nikolic. Copyright
Modified From "Digital Integrated Circuits", by1996
J. Rabaey,
UCB A. Chandrakasan and B. Nikolic
NMOS transistor, logic 1
Modified From "Digital Integrated
Circuits", by J. Rabaey, A.
Chandrakasan and B. Nikolic. Copyright
Modified From "Digital Integrated Circuits", by1996
J. Rabaey,
UCB A. Chandrakasan and B. Nikolic
NMOS transistor, logic 1
Modified From "Digital Integrated
Circuits", by J. Rabaey, A.
Chandrakasan and B. Nikolic. Copyright
Modified From "Digital Integrated Circuits", by1996
J. Rabaey,
UCB A. Chandrakasan and B. Nikolic
PMOS transistors
Modified From "Digital Integrated
Circuits", by J. Rabaey, A.
Chandrakasan and B. Nikolic. Copyright
Modified From "Digital Integrated Circuits", by1996
J. Rabaey,
UCB A. Chandrakasan and B. Nikolic
Example of the process
Modified From "Digital Integrated
Circuits", by J. Rabaey, A.
Chandrakasan and B. Nikolic. Copyright
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UCB A. Chandrakasan and B. Nikolic
Cascades
Modified From "Digital Integrated
Circuits", by J. Rabaey, A.
Chandrakasan and B. Nikolic. Copyright
Modified From "Digital Integrated Circuits", by1996
J. Rabaey,
UCB A. Chandrakasan and B. Nikolic
Cascades
Modified From "Digital Integrated
Circuits", by J. Rabaey, A.
Chandrakasan and B. Nikolic. Copyright
Modified From "Digital Integrated Circuits", by1996
J. Rabaey,
UCB A. Chandrakasan and B. Nikolic
Equivalent output resistance: Short channel
ID
V GS = VDD
V DS
VDD/2
Integrar la curva hasta Vdsat utilizando
VDD
W
I Dsat  K
L
2

VDsat 
 (Vdd  VT )VDsat 



2


Modified From "Digital Integrated
Circuits", by J. Rabaey, A.
Chandrakasan and B. Nikolic. Copyright
Modified From "Digital Integrated Circuits", by1996
J. Rabaey,
UCB A. Chandrakasan and B. Nikolic
Equivalent switching resistance


AMI 0.5um; S=3; K=54e-6; Ec L = 0.9V
Resistance is inversely
VT = 0.5V
proportional to W/L
For Vdd bigger than VT+Vdsat/2,
R becomes independent of the
supply voltage

Limit value:
Rlim 

1
1
2 log(2) K  S  VDSAT
If supply voltage approaches VT
resistance increases dramatically
Vt
Vdsat
Modified From "Digital Integrated
Circuits", by J. Rabaey, A.
Chandrakasan and B. Nikolic. Copyright
Modified From "Digital Integrated Circuits", by1996
J. Rabaey,
UCB A. Chandrakasan and B. Nikolic
Qualitative Analysis



Response dominated by the output capacitance
A fast gate has small output C or small resistance (increase
W/L)
Notice that output resistance of the switch is not constant !!
Modified From "Digital Integrated
Circuits", by J. Rabaey, A.
Chandrakasan and B. Nikolic. Copyright
Modified From "Digital Integrated Circuits", by1996
J. Rabaey,
UCB A. Chandrakasan and B. Nikolic
(CMOS) Important Properties





High and low levels are VDD and GND (high noise margins)
Logic levels are independent of device sizes (ratioless)
Steady-state finite resistance path between VDD or GND and
output (low output resistance)
Zero DC input current: A single inverter can theoretically drive
an infinite number of gates …
No steady-state direct current path between VDD and GND
(no static power consumption)
Modified From "Digital Integrated
Circuits", by J. Rabaey, A.
Chandrakasan and B. Nikolic. Copyright
Modified From "Digital Integrated Circuits", by1996
J. Rabaey,
UCB A. Chandrakasan and B. Nikolic
Design for Performance
Modified From "Digital Integrated
Circuits", by J. Rabaey, A.
Chandrakasan and B. Nikolic. Copyright
Modified From "Digital Integrated Circuits", by1996
J. Rabaey,
UCB A. Chandrakasan and B. Nikolic
Computing capacitances: Input

(GD) Cgd by Miller appears a
2Cgd at the input and the output

Also Cgs and Cgd
Wiring (include if noticeable)

Cin  (CGS n  2CGDn  CGn )  (CGS p  2CGD p  CGp )  CW in

Assuming M1 and M2 are saturated Cg=Cgs=2/3 WLCox
2
2
Cin  ( CoxWn Ln  2CGDon  CGSon )  ( CoxWn Ln  2CGDo p  CGSo p )  CW in
3
3
Modified From "Digital Integrated
Circuits", by J. Rabaey, A.
Chandrakasan and B. Nikolic. Copyright
Modified From "Digital Integrated Circuits", by1996
J. Rabaey,
UCB A. Chandrakasan and B. Nikolic
Computing capacitances: Output


(GD) overlap at the output due to
Miller
(DB) Drain Diffusions


Cdb has to be linearized
Wiring
Cout  (2CGDn  CDBn )  (2CGD p  CDBp )  CW out
Modified From "Digital Integrated
Circuits", by J. Rabaey, A.
Chandrakasan and B. Nikolic. Copyright
Modified From "Digital Integrated Circuits", by1996
J. Rabaey,
UCB A. Chandrakasan and B. Nikolic
Computing capacitances: Inverter Load

Fan out capacitance:

M3/M4 do not change mode until
Vout reaches 50% (Vout2 is
constant). No Miller
 Cox changes (one saturated and
one in cut-off). It is approximated
for the worst case (10% error)
CL  (CGS n  CGDn  CGn )  (CGS p  CGD p  CGp )
CL  (CGS n  CGDn  Wn LnCox )  (CGS p  CGD p  CGp  W p L pCox )
Modified From "Digital Integrated
Circuits", by J. Rabaey, A.
Chandrakasan and B. Nikolic. Copyright
Modified From "Digital Integrated Circuits", by1996
J. Rabaey,
UCB A. Chandrakasan and B. Nikolic
Example

Minimum size inverter in 0.25µm


NMOS: 3λ/2λ (0.375/0.25);
Capacitances:

Cgson=0.115fF;
 Cgsop=0.305fF;
 Cdbn=0.8fF;
 WLCoxn=0.53fF;

PMOS: 9λ/2λ (1.125/0.25)
Cgdon=0.115fF;
Cgdop=0.305fF;
Cdbp=1.35fF;
WLCoxp=1.67fF;
Inverter capacitances

Cin=2.72fF
 Cout=2.68
 CL=3.04fF
2.72
fF
Modified From "Digital
Integrated
5.72 fF
Circuits", by J. Rabaey, A.
Chandrakasan and B. Nikolic. Copyright
Modified From "Digital Integrated Circuits", by1996
J. Rabaey,
UCB A. Chandrakasan and B. Nikolic
Computing Capacitances: Pass Transistor

From the gate:

If output does not change



If output changes



Cg=Cgso+Cgdo+WLCox
Triode
Cg=Cgso+2Cgdo+(2/3) WLCox
Cav=Cgso+1.5 Cgdo+1.5 WLCox
From the S/D terminal

If gate is ON



1 ->0: Cin=Cgso+Cdiff+(2/3) WL Cox
 During the transition the transistor is in saturation and we drive the source
0->1: Cin=Cgso+Cdiff
 During the transition the transistor is in saturation and we drive the drain
If gate is OFF

Cin=Cgso+Cdiff
Modified From "Digital Integrated
Circuits", by J. Rabaey, A.
Chandrakasan and B. Nikolic. Copyright
Modified From "Digital Integrated Circuits", by1996
J. Rabaey,
UCB A. Chandrakasan and B. Nikolic
Design for Performance



Keep capacitances (internal, interconnect and fan-out) small
by good layout
Increase transistor sizes
 watch out for self-loading! Once that the intrinsic
capacitance dominates the delay, W/L does not help
anymore
Increase VDD (????):


There are limits to the maximum.
Increases power consumption
Modified From "Digital Integrated
Circuits", by J. Rabaey, A.
Chandrakasan and B. Nikolic. Copyright
Modified From "Digital Integrated Circuits", by1996
J. Rabaey,
UCB A. Chandrakasan and B. Nikolic
Delay as a function of VDD
5.5
5
tp(normalized)
4.5
4
3.5
3
The shape of this curve is
the same as R vs. VDD
2.5
2
1.5
1
0.8
1
1.2
1.4
1.6
V
1.8
2
2.2
2.4
(V)
DD
Smaller VDD implies smaller
current
Id, and slower transition
Modified From
"Digital Integrated
Circuits", by J. Rabaey, A.
Chandrakasan and B. Nikolic. Copyright
Modified From "Digital Integrated Circuits", by1996
J. Rabaey,
UCB A. Chandrakasan and B. Nikolic
NMOS/PMOS ratio
If a symmetrical characteristic is not
important, inverter can be optimized for
speed by reducing the P-size. Design
variable:
 = Wp/Wn
Considering two identical cascaded inverters:


Cw
 0  opt  r 1 
 Cdn1  Cgn 2 



t p
If Cw<<C, then optimum factor is
sqrt(r) instead of r (symm. swing)
CL  (Cdp1  Cdn1 )  (Cdp 2  Cdn 2 )  Cw
-11
5
x 10
CL  (1   )(Cdn1  Cgn 2 )  Cw
r  Reqp / Reqn   p / n
tpHL
tpLH
tp(sec)
Cdp1   Cdn1 , Cgp 2   Cgn 2 , Rp  Reqp /  ,
4.5
4
tp
3.5
tp

r
(1   )(Cdn1  Cgn 2 )  Cw  R eq 1  
3

1

Modified From "Digital Integrated
1.5
2
2.5
3

Circuits", by J. Rabaey, A.
Chandrakasan and B. Nikolic. Copyright
Modified From "Digital Integrated Circuits", by1996
J. Rabaey,
UCB A. Chandrakasan and B. Nikolic
3.5
4
4.5
5
Device Sizing

Assuming a symmetrical inverter, the capacitance is composed of:
CL  Cint  Cext


Cint is the self-load, associated with diffusion and gate-drain (Miller)
Cext is extrinsec, load, wiring, etc.
t p  0.69 Req (Cint  Cext )  t p 0 (1  Cext / Cint )
t p 0  0.69 Req Cint

Where
is the intrinsec delay (Cext=0)

What are the consequences of scaling ?
Modified From "Digital Integrated
Circuits", by J. Rabaey, A.
Chandrakasan and B. Nikolic. Copyright
Modified From "Digital Integrated Circuits", by1996
J. Rabaey,
UCB A. Chandrakasan and B. Nikolic
Device Sizing

Cint scales with size ratio S, and also Req:
Cint  SCiref ,

The delay is:
Req  Riref / S ,
t p  t p 0 (1  Cext / SCiref )
• The intrinsic delay is independent of sizing and is determined by
technology and layout.
• Making S infinitely large gives the maximum performance gain,
eliminating the impact of an external load. Yet, a big enough sizing
produces similar results with a gain in Silicon area
• A big inverter has big input capacitance and affects the previous stages !
Modified From "Digital Integrated
Circuits", by J. Rabaey, A.
Chandrakasan and B. Nikolic. Copyright
Modified From "Digital Integrated Circuits", by1996
J. Rabaey,
UCB A. Chandrakasan and B. Nikolic
Device Sizing
-11
3.8
x 10
(for fixed load)
3.6
3.4
tp(sec)
3.2
3
2.8
Self-loading effect:
Intrinsic capacitances
dominate
2.6
2.4
2.2
2
2
4
6
8
S
10
12
14
Modified From "Digital Integrated
Circuits", by J. Rabaey, A.
Chandrakasan and B. Nikolic. Copyright
Modified From "Digital Integrated Circuits", by1996
J. Rabaey,
UCB A. Chandrakasan and B. Nikolic
Inverter Chain Sizing
Modified From "Digital Integrated
Circuits", by J. Rabaey, A.
Chandrakasan and B. Nikolic. Copyright
Modified From "Digital Integrated Circuits", by1996
J. Rabaey,
UCB A. Chandrakasan and B. Nikolic
Inverter Chain
In
Out
CL
If CL is given:
- How many stages are needed to minimize the delay?
- How to size the inverters?
May need some additional constraints.
Modified From "Digital Integrated
Circuits", by J. Rabaey, A.
Chandrakasan and B. Nikolic. Copyright
Modified From "Digital Integrated Circuits", by1996
J. Rabaey,
UCB A. Chandrakasan and B. Nikolic
Inverter Delay


Minimum length devices, L
Assume the same electrical
characteristics
2W

Wn = 2 Wp
 approx. equal rise tpLH and fall
tpHL delays
W
Delay (D): tpHL = k RNCL
tpLH = k RPCL
Modified From "Digital Integrated
Circuits", by J. Rabaey, A.
Chandrakasan and B. Nikolic. Copyright
Modified From "Digital Integrated Circuits", by1996
J. Rabaey,
UCB A. Chandrakasan and B. Nikolic
Delay Formula
Delay ~ RW Cint  C L 
t p  kRW Cint 1  C L / Cint   t p 0 1  f /  
Cint =  Cgin with   1
Inverter 0.25µm
γ=2.68/2.72=0.98
f = CL / Cgin - effective fanout
Delay is only a function of the ratio between its external load capacitance and its
input capacitance
Modified From "Digital Integrated
Circuits", by J. Rabaey, A.
Chandrakasan and B. Nikolic. Copyright
Modified From "Digital Integrated Circuits", by1996
J. Rabaey,
UCB A. Chandrakasan and B. Nikolic
Apply to Inverter Chain
In
Out
1
2
N
CL
tp = tp1 + tp2 + …+ tpN
 C gin, j 1 

t pj ~ RunitCunit 1 
 C

gin
,
j


N
N 
C gin, j 1 
, C gin, N 1  C L
t p   t p , j  t p 0  1 
 "Digital


C
Modified
Integrated
j 1
i 1From
gin
,
j


Circuits", by J. Rabaey, A.
Chandrakasan and B. Nikolic. Copyright
Modified From "Digital Integrated Circuits", by1996
J. Rabaey,
UCB A. Chandrakasan and B. Nikolic
Optimal Tapering for Given N
Delay equation has N - 1 unknowns, Cgin,2 – Cgin,N
Minimize the delay, find N - 1 partial derivatives
Result: Cgin,j+1/Cgin,j = Cgin,j/Cgin,j-1
- each stage has the same effective fanout (Cout/Cin)
- each stage has the same delay
Size of each stage is the geometric mean of two neighbors
C gin, j  C gin, j 1C gin, j 1
Modified From "Digital Integrated
Circuits", by J. Rabaey, A.
Chandrakasan and B. Nikolic. Copyright
Modified From "Digital Integrated Circuits", by1996
J. Rabaey,
UCB A. Chandrakasan and B. Nikolic
Optimum Delay and Number of Stages
When each stage is sized by f and has same eff. fanout f:
f N  F  CL / Cgin,1
Effective fanout of each stage:
f NF
Minimum path delay

t p  Nt p 0 1  N F / 

Modified From "Digital Integrated
Circuits", by J. Rabaey, A.
Chandrakasan and B. Nikolic. Copyright
Modified From "Digital Integrated Circuits", by1996
J. Rabaey,
UCB A. Chandrakasan and B. Nikolic
Example
In
C1
Out
1
f
f2
CL= 8 C1
CL/C1 has to be evenly distributed across N = 3 stages:
f 38 2
Modified From "Digital Integrated
Circuits", by J. Rabaey, A.
Chandrakasan and B. Nikolic. Copyright
Modified From "Digital Integrated Circuits", by1996
J. Rabaey,
UCB A. Chandrakasan and B. Nikolic
Optimum Number of Stages
For a given load, CL and given input capacitance Cin
Find optimal sizing f
ln F
N
CL  F  Cin  f Cin with N 
ln f

f  t p 0 ln F  f
 
t p  Nt p 0 1   





ln
f
ln
f




f that minimizes total delay results from:
t p
f

t p 0 ln F ln f  1   f

0
2

ln f
f  exp 1   f 
Modified From "Digital Integrated
Circuits", by J. Rabaey, A.
Chandrakasan and B. Nikolic. Copyright
Modified From "Digital Integrated Circuits", by1996
J. Rabaey,
UCB A. Chandrakasan and B. Nikolic
Optimum Effective Fanout f
Optimum f for given process defined by g
f  exp 1   f 
fopt = 3.6
for =1
For  = 0, f = e, N = lnF
Modified From "Digital Integrated
Circuits", by J. Rabaey, A.
Chandrakasan and B. Nikolic. Copyright
Modified From "Digital Integrated Circuits", by1996
J. Rabaey,
UCB A. Chandrakasan and B. Nikolic
Trade-offs in the choice of N


Number of stages large, intrinsic delay dominates
Too small, the effective fan-out dominates
t p  Nt p 0 1  f /   ,


N
log( F )
log( f )
With more stages (smaller f), N grows exponencially and f decreases
linearly: tp increases
With fewer stages (bigger f), N reduces and f increases: tp remains
roughly constant
Modified From "Digital Integrated
Circuits", by J. Rabaey, A.
Chandrakasan and B. Nikolic. Copyright
Modified From "Digital Integrated Circuits", by1996
J. Rabaey,
UCB A. Chandrakasan and B. Nikolic
Choice of N: Example


t p  Nt p 0 1  N F / 
Example: Ci=1fF, Cout=1pF:
F=1000

tp (normalized delay)
N (number of stages)
f
From "Digital
Integrated
Make f slightly larger thanModified
optimum
(to
round
off stages. Typ.=4)
Circuits", by J. Rabaey, A.
Chandrakasan and B. Nikolic. Copyright
Modified From "Digital Integrated Circuits", by1996
J. Rabaey,
UCB A. Chandrakasan and B. Nikolic
f
Normalized delay function of F

Values of tp/Optimum(tp) for several designs
F
Unbuffered
Two Stage
Inverter chain
10
11
8.3
8.3
100
101
22
16.5
1000
1001
65
24.8
10,000
10,001
202
33.1
Modified From "Digital Integrated
Circuits", by J. Rabaey, A.
Chandrakasan and B. Nikolic. Copyright
Modified From "Digital Integrated Circuits", by1996
J. Rabaey,
UCB A. Chandrakasan and B. Nikolic
Buffer Design
1
f
tp
1
64
65
2
8
18
64
3
4
15
64
4
2.8
15.3
64
1
8
1
4
16
2.8
8
1
N
64
22.6
Modified From "Digital Integrated
Circuits", by J. Rabaey, A.
Chandrakasan and B. Nikolic. Copyright
Modified From "Digital Integrated Circuits", by1996
J. Rabaey,
UCB A. Chandrakasan and B. Nikolic
Impact of Rise Time on Delay
0.35
tpHL(nsec)
0.3
0.25
0.2
0.15
0
0.2
0.4
0.6
trise (nsec)
0.8
1
Modified From "Digital Integrated
Circuits", by J. Rabaey, A.
Chandrakasan and B. Nikolic. Copyright
Modified From "Digital Integrated Circuits", by1996
J. Rabaey,
UCB A. Chandrakasan and B. Nikolic
Practical Rules


Keep signal rise times smaller than or equal to gate
propagation delays (for both performance and power
consumption)
Keep rise and fall times small and of similar values (challenge
known as slope engineering)
Modified From "Digital Integrated
Circuits", by J. Rabaey, A.
Chandrakasan and B. Nikolic. Copyright
Modified From "Digital Integrated Circuits", by1996
J. Rabaey,
UCB A. Chandrakasan and B. Nikolic
Power Dissipation
Modified From "Digital Integrated
Circuits", by J. Rabaey, A.
Chandrakasan and B. Nikolic. Copyright
Modified From "Digital Integrated Circuits", by1996
J. Rabaey,
UCB A. Chandrakasan and B. Nikolic
Where Does Power Go in CMOS?
• Dynamic Power Consumption
Charging and Discharging Capacitors
• Short Circuit Currents
Short Circuit Path between Supply Rails during Switching
• Leakage
Leaking diodes and transistors
Modified From "Digital Integrated
Circuits", by J. Rabaey, A.
Chandrakasan and B. Nikolic. Copyright
Modified From "Digital Integrated Circuits", by1996
J. Rabaey,
UCB A. Chandrakasan and B. Nikolic
Dynamic Power Dissipation
Vdd
Vin
Vout
CL

EVdd

Vdd
dvout
  iVdd (t )Vdd dt Vdd  CL
dt CL  dvout CLVdd 2
dt
0
0
0


Vdd
dvout
CLVdd 2
EC   iVdd (t )vout dt  CL
vout dt CL  vout dvout 
dt
2
0
0
0
Modified From "Digital Integrated
Circuits", by J. Rabaey, A.
Chandrakasan and B. Nikolic. Copyright
Modified From "Digital Integrated Circuits", by1996
J. Rabaey,
UCB A. Chandrakasan and B. Nikolic
Dynamic Power Dissipation
Vdd
Vin
Vout
CL
2
dd
L
Energy/transition = C * V
L
Power = Energy/transition * f = C * V
2
dd
*f
Not a function of Ltransistor
sizes!
dd
Need to reduce C , V , and f to reduce power.
Modified From "Digital Integrated
J. Rabaey,
Dependence with Circuits",
supplybyvoltage
isA.quadratic !!!
Chandrakasan and B. Nikolic. Copyright
Modified From "Digital Integrated Circuits", by1996
J. Rabaey,
UCB A. Chandrakasan and B. Nikolic
Node Transition Activity and Power
Consider switching a CMOS gate for N clock cycles
E N = CL  V dd2  n N 
EN : the energy consumed for N clock cycles
n(N ): the number of 0->1 transition in N clock cycles
EN
2
n N 
P avg = lim --------  fclk =  lim ----------- C  Vdd  f clk
N   N 
N N
L
0  1 =
n N 
lim -----------N N
P avg = 0 1  C  Vdd 2  f clk

L
Modified From "Digital Integrated
Circuits", by J. Rabaey, A.
Chandrakasan and B. Nikolic. Copyright
Modified From "Digital Integrated Circuits", by1996
J. Rabaey,
UCB A. Chandrakasan and B. Nikolic
Short Circuit Currents
Vd d
I peak is a function of
transistor sizes.
Vout
Vin
CL
It is also a strong
function of the input and
output slopes …
0.15
IVDD (mA)
1
t
2
P  K (Vdd  VT ) Vdd
2
T
0.10
Reading Material
0.05
0.0
CMOS Circuit Speed and Buffer Optimization
Hedenstierna, N.; Jeppson, K.O.;
Computer-Aided Design of Integrated Circuits and Systems,
1.0
3.0
2.0
Vin (V)
4.0
5.0
IEEE Transactions on
Volume 6, Issue 2, March 1987 Page(s):270 - 281
Modified From "Digital Integrated
Circuits", by J. Rabaey, A.
Chandrakasan and B. Nikolic. Copyright
Modified From "Digital Integrated Circuits", by1996
J. Rabaey,
UCB A. Chandrakasan and B. Nikolic
Short Circuit Currents
Vdd
Vin
Vout
CL

If the output is too slow, then the P transistor is off and there’s
no direct current
Modified From "Digital Integrated
Circuits", by J. Rabaey, A.
Chandrakasan and B. Nikolic. Copyright
Modified From "Digital Integrated Circuits", by1996
J. Rabaey,
UCB A. Chandrakasan and B. Nikolic
Short Circuit Current
Vdd
Vin
Vout
CL

If the output is too fast, then the P transistor goes quickly to
saturation (Vds = Vcc) and power consumption is maximum
Modified From "Digital Integrated
Circuits", by J. Rabaey, A.
Chandrakasan and B. Nikolic. Copyright
Modified From "Digital Integrated Circuits", by1996
J. Rabaey,
UCB A. Chandrakasan and B. Nikolic
Short Circuit Current

Graph of direct current versus
output capacitance

Short circuit current goes to zero
if tfall >> trise, but can’t do this
for cascade logic, so ...
Modified From "Digital Integrated
Circuits", by J. Rabaey, A.
Chandrakasan and B. Nikolic. Copyright
Modified From "Digital Integrated Circuits", by1996
J. Rabaey,
UCB A. Chandrakasan and B. Nikolic
How to keep Short-Circuit Currents Low?

Graph of power dissipation
versus output capacitance
for various rise times (fixed
freq. and Vdd)
Modified From "Digital Integrated
Circuits", by J. Rabaey, A.
Chandrakasan and B. Nikolic. Copyright
Modified From "Digital Integrated Circuits", by1996
J. Rabaey,
UCB A. Chandrakasan and B. Nikolic
Minimizing Short-Circuit Power
8
7
6
Vdd =3.3
Pnorm
5
4
Vdd =2.5
3
2
1
Vdd =1.5
0
0
1
2
3
4
5
t /t
sin sout
Modified From "Digital Integrated
Circuits", by J. Rabaey, A.
Chandrakasan and B. Nikolic. Copyright
Modified From "Digital Integrated Circuits", by1996
J. Rabaey,
UCB A. Chandrakasan and B. Nikolic
Leakage
Vd d
Vout
Drain Junction
Leakage
Sub-Threshold
Current
Sub-threshold
current one of most
compelling
issues
Sub-Threshold
Current
Dominant
Factor
in low-energy circuit design!
Modified From "Digital Integrated
Circuits", by J. Rabaey, A.
Chandrakasan and B. Nikolic. Copyright
Modified From "Digital Integrated Circuits", by1996
J. Rabaey,
UCB A. Chandrakasan and B. Nikolic
Reverse-Biased Diode Leakage
GATE
p+
p+
N
Reverse Leakage Current
+
V
- dd
IDL = JS  A
2
JS = JS
1-5pA/
for a 1.2
technology
= 10-100
at 25
degCMOS
C for 0.25m
CMOS
mpA/m2
m
JS doubles for every 9 deg C!
Modified
From
"Digital
Integrated
Js double with
every
9oC
increase
in temperature
Circuits", by J. Rabaey, A.
Chandrakasan and B. Nikolic. Copyright
Modified From "Digital Integrated Circuits", by1996
J. Rabaey,
UCB A. Chandrakasan and B. Nikolic
Subthreshold Leakage Component
Modified From "Digital Integrated
Circuits", by J. Rabaey, A.
Chandrakasan and B. Nikolic. Copyright
Modified From "Digital Integrated Circuits", by1996
J. Rabaey,
UCB A. Chandrakasan and B. Nikolic
Static Power Consumption
Vd d
Istat
Vout
Vin =5V
CL
Pstat = P(In=1) .Vdd . Istat
Wasted energy
…
• Dominates
over dynamic consumption
Should be avoided in almost all cases,
Not areducing
function
of switching
but could• help
energy
in othersfrequency
(e.g. sense amps)
Modified From "Digital Integrated
Circuits", by J. Rabaey, A.
Chandrakasan and B. Nikolic. Copyright
Modified From "Digital Integrated Circuits", by1996
J. Rabaey,
UCB A. Chandrakasan and B. Nikolic
Energy and Energy-Delay
Power-Delay Product (PDP) =
E = Energy per operation = Pav  tp
Energy-Delay Product (EDP) =
quality metric of gate = E  tp
Modified From "Digital Integrated
Circuits", by J. Rabaey, A.
Chandrakasan and B. Nikolic. Copyright
Modified From "Digital Integrated Circuits", by1996
J. Rabaey,
UCB A. Chandrakasan and B. Nikolic
Power Delay Product or Energy/Operation

The PDP is a measure of Energy
PDP  Pavt p

Assuming that the gate is switched at the maximum possible rate of
f max  1 / 2t p

PDP gives the average energy per switching event
CLVdd 2
PDP 
2
Modified From "Digital Integrated
Circuits", by J. Rabaey, A.
Chandrakasan and B. Nikolic. Copyright
Modified From "Digital Integrated Circuits", by1996
J. Rabaey,
UCB A. Chandrakasan and B. Nikolic
Energy-Delay Product (EDP)


PDP is questionable as a performance index. A low supply gives a
reduced PDP but at the cost of speed.
EDP measures energy and performance:
EDP  PDP  t p
CLVdd 2
EDP 
tp
2
Energy
Energy-Delay
Delay
0.5
Modified From "Digital Integrated 2.5
1.2by J. Rabaey, A.
Circuits",
Vdd
Chandrakasan and B. Nikolic. Copyright
Modified From "Digital Integrated Circuits", by1996
J. Rabaey,
UCB A. Chandrakasan and B. Nikolic
Principles for Power Reduction

Prime choice: Reduce voltage!




Recent years have seen an acceleration in supply voltage reduction
Design at very low voltages still open question (0.6 … 0.9 V by
2010!)
Reduce switching activity
Reduce physical capacitance
Modified From "Digital Integrated
Circuits", by J. Rabaey, A.
Chandrakasan and B. Nikolic. Copyright
Modified From "Digital Integrated Circuits", by1996
J. Rabaey,
UCB A. Chandrakasan and B. Nikolic
Appendix
Short Channel model
© Digital Integrated Circuits2nd
Modified From "Digital Integrated
Circuits", by J. Rabaey, A.
Chandrakasan and B. Nikolic. Copyright
1996 UCB
Inverter
Short Channel Model

Short channel model
I D  eff Cox S
 eff E
,

v  1  E / Ec
v ,
 sat
1
1  VDS / Ec L
E  Ec
E  Ec
(VGT  VDS / 2)VDS

Vdsat is no longer Vgt=Vg-Vt, but:

For small Vgt, Vdsat=Vgt and coincides with the long channel case
For bigger drives (Vgt), Vdsat reaches a limit value of Vdsat=Ec L

Ec LVGT
Vdsat 
Ec L  VGT
Modified From "Digital Integrated
Circuits", by J. Rabaey, A.
Chandrakasan and B. Nikolic. Copyright
Modified From "Digital Integrated Circuits", by1996
J. Rabaey,
UCB A. Chandrakasan and B. Nikolic
Triode and saturation region
Ec L
Id
Ec LVGT
Vdsat 
Ec L  VGT
triode
Vel. saturation
Modified From "Digital Integrated
Circuits", by J. Rabaey, A.
Chandrakasan and B. Nikolic. Copyright
Modified From "Digital Integrated Circuits", by1996
J. Rabaey,
UCB A. Chandrakasan and B. Nikolic
Vds
Transfer characteristic
Id
cuadratic
linear
Modified From "Digital Integrated Asymptote: Vt+EcL/2
Circuits", by J. Rabaey, A.
Chandrakasan and B. Nikolic. Copyright
Modified From "Digital Integrated Circuits", by1996
J. Rabaey,
UCB A. Chandrakasan and B. Nikolic
Vg
Digital case

For the digital case, Vgt is generally big, therefore:
I D  KS (VGT

1
 VDSAT )VDSAT
2
Vdsat  Ec L
Referencias:


Sodini C. G., P. Ko, J. L. Moll, “The effect of high fields on MOS
device and circuit performance,” IEEE Trans. El. Devices, Vol. ED31,
No. 10, Oct. 1984, pp. 1386-1393.
Toh K., Ko P., Meyer R. G., “An engineering model for short-channel
MOS devices,” IEEE J. Solid state circuits, Vol. 23, No. 4. August
1988, pp. 950-958.
Modified From "Digital Integrated
Circuits", by J. Rabaey, A.
Chandrakasan and B. Nikolic. Copyright
Modified From "Digital Integrated Circuits", by1996
J. Rabaey,
UCB A. Chandrakasan and B. Nikolic