Download Enterprise Ethernet Switch/Routers using PowerPC

Confidential & Proprietary
PRELIMINARY MATERIAL
440GP
Part Number 440GP
Revision 1.01 – September 7, 2004
Preliminary Application Note
Enterprise Ethernet Switch/Routers using PowerPC Processors
INTRODUCTION
Ethernet has become today’s standard for local area networks worldwide. The development of Layer 2 switching
for Ethernet, followed by the development of Fast Ethernet (100 Mbps), full-duplex Ethernet, Layer 3 switching
(which is routing applied to switching), and Gigabit Ethernet have resulted in the dominance of Ethernet as a local
area network (LAN) technology. The addition of 10-Gigabit/second Ethernet has further secured Ethernet’s place in
the networking world.
This application note looks at using AMCC PowerPC™ processors as the control plane processors in enterprise
Ethernet switches. Beginning with an overview of Ethernet switching technology, the discussion continues with an
overview of the AMCC PowerPC 440GP and 440GX embedded processors and the IBM PowerPC 750FX and
750CXe microprocessors with the Discovery II family of system controllers from Marvell. The highly integrated
440GP and 440GX processors with their high-speed interfaces are ideally suited to provide control plane functionality in many of today’s enterprise Ethernet switches. The powerful 750FX and 750CXe processors in conjunction
with the high performance Discovery II system controllers are very well suited for mid-range to high-end switch systems. An overview of the different categories and types of switches available in the enterprise Ethernet switch
market is also discussed. Following, is a review of some block diagrams of possible enterprise Ethernet switch/
router implementations using the AMCC PowerPC processors. This application note concludes with an overview of
the comprehensive software support that is available for enterprise Ethernet switches and the AMCC PowerPC
family from LVL7 Systems, Inc. (LVL7).
ETHERNET SWITCHING TECHNOLOGY
Layer 2 switching actually means another Layer 2 operation: bridging. The primary differences are that a switch
has hardware-based frame processing and a backplane that interconnects all the ports and allows multiple simultaneous temporary connections between the LAN segments for the forwarding and filtering of frames.
Many Ethernet switches also support the concept of a virtual LAN (VLAN). A virtual LAN is a logical grouping of
local area network nodes that share a common broadcast domain without crossing a router. The LAN nodes can be
organized into VLANs by:
•
•
•
•
•
The switch port to which they are connected
Their MAC addresses
The protocols that the nodes use
IP network or subnet addresses
A multicast address
The goals of VLANs are to control broadcasts, which can increase available network bandwidth, and to group the
nodes into groups that make logical sense. For example, people who are in the same department, have the same
jobs, or share common resources (servers, printers, and so on).
Layer 3 switching is another name for combining VLAN switching with Layer 3 (usually IP/IPX) routing and adding
both of them with the appropriate hardware support onto a Layer 2 switch device. This type of device is often
referred to as a switch/router.
Layer 4 switching is way of using Layer 4 information, such as TCP and UDP port numbers, to switch or filter
(deny) traffic based on the application. Traffic can also be classified by the application, and policies can be applied
to give priority of some traffic over other traffic.
Much of the hardware support for Layer 2, 3, and 4 switching is provided today by application-specific integrated
circuits (ASICs) or application-specific standard products (ASSPs). ASICs and ASSPs are specialized integrated
circuits designed to perform a particular application very well. The speeds and functionality of these switching
ASICs/ASSPs are increasing steadily due to the improvements in semiconductor design and manufacturing.
AMCC Confidential and Proprietary
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440GP – Enterprise Ethernet Switch/Routers
using PowerPC Processors
Revision 1.01 – September 7, 2004
Preliminary Application Note
SWITCH DATA PLANE AND CONTROL PLANE OPERATION
Ethernet frames have a source address (SA) and a destination address (DA). The Layer 2 Ethernet switch hardware learns the location of a network station from the source address field in an incoming frame and the switch port
where the frame was received. The switch builds a forwarding table that contains the source address, the switch
port where it is located, and an age. The oldest entries in the table are removed (aged out) to make room for new
entries. The forwarding table enables the switch to forward incoming frames to the correct outbound switch port
where the destination address is located.
The switch also communicates with other switches using the spanning tree algorithm (IEEE 802.1D standard) to
prevent loops in the network from continually repeating broadcast traffic and causing broadcast storms.
For Layer 3 switching, the switch is a Layer 3 router and therefore communicates with the other routers in the network using a routing protocol (such as RIP, OSPF, and so on). These routing protocols allow the switch to build the
routing tables that enable it to route packets to the correct outbound port and the correct “next hop” router.
A well-designed switch is able to forward almost all the frames with valid SA and DA addresses. However, there
will be frames for destinations that are “unknown” (the destination does not appear in the switch forwarding or routing tables) or frames that might require special intervention. In these cases, the frames are sent to the control plane
processor. The control plane processor determines how the unknown frames should be processed and performs
any resulting table updates to the switch hardware. The control plane processor also frequently updates the tables
in the switch hardware based on the output of the routing protocols that are running on the processor. In addition to
processing the unknowns and executing the routing protocols, the control plane processor is also used to configure
the switch, to maintain switching/routing and network statistics and to interact with the network management system (NMS). The switch interacts with the NMS by responding to queries and by issuing traps (alerts). The control
plane processor can also be used to perform other functions in software that are not supported by the switch hardware. These functions could include QoS, bandwidth reservation, or multicast support.
OVERVIEW OF THE AMCC POWERPC 440GP, 440GX, AND 750FX/CXE PROCESSORS
The AMCC PowerPC 440GP processor (see Figure 1) is a 32-bit implementation of the Book E enhanced PowerPC architecture, which supports frequencies of 400, 466, and 500 MHz with 2.0 Dhrystone 2.1 MIPS/MHz. A
PowerPC 440 core utilizes a 7-stage pipeline and executes up to two instructions per clock cycle. The core
includes a 32-KB data cache and 32-KB instruction cache, each of which is 64-way set associative. The on-chip
DDR SDRAM memory controller supports 32-bit or 64-bit interfaces with optional ECC for 64-, 128-, and 256-Mb
DDR devices from DDR200 to DDR266 with a peak data rate of 2.1 Gbps. A PCI-X interface supports 32-bit or 64bit PCI-X V1.0 at up to 133 MHz, or 32-bit or 64-bit PCI V2.0 at up to 66 MHz. An external bus controller supports
external data bus widths of 8, 16, or 32 bits and a 32-bit address bus. This controller can support up to eight ROM,
EPROM, SRAM, Flash, or slave peripheral I/O devices. The DMA controller provides four DMA channels and scatter/gather capability. On-chip Ethernet support includes two 10/100 Ethernet MACs supporting one MII, two RMII,
or two SMII ports. Other features include: 8-KB SRAM, two serial ports, two IIC controllers, 32 GPIO, 13 external
interrupts, and general-purpose timers. Debug support is provided via JTAG, RISCWatch, and RISCTrace support.
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AMCC Confidential and Proprietary
Revision 1.01 – September 7, 2004
440GP – Enterprise Ethernet Switch/Routers
using PowerPC Processors
Preliminary Application Note
Figure 1. AMCC PowerPC 440GP Embedded Processor Block Diagram
Arbiter
PCI-X
Bridge
128-Bit
Processor Local Bus (PLB)
32 K
I-Cache
32 K
D-Cache
SRAM
Control
8 KB
SRAM
MMU
OPB
Bridge
Interrupt
Control
RAM/ROM
Peripheral
Controller
Ext. Bus
Master
Controller
IIC (2)
UART (2)
GPIO
DMA
Controller
32-Bit
440 CPU
PLB
Monitor
On-Chip Peripheral Bus (OPB)
DDR SDRAM
Controller
JTAG Trace Timers
Arbiter
GPT
10/100
Ethernet
MAC (2)
PowerPC 440 Core
The AMCC PowerPC 440GX processor (see Figure 2) is also a 32-bit implementation of the Book E enhanced
PowerPC architecture, that supports frequencies of 500 to 667 MHz with 2.0 Dhrystone 2.1 MIPS/MHz.
The 440GX processor has the same architecture as the 440GP with the following changes:
•
•
•
•
256 KB of on-chip SRAM, which is configurable as L2 cache or packet/code-store memory.
Two 10/100/1 GB Ethernet MACs with jumbo frame support and TCP/IP acceleration hardware (TAH) are
included in addition to the two 10/100 Ethernet MACs from the 440GP. Either two SMII, two RGMII/RTBI or
one GMII/TBI interface are supported. The TAH supports checksum generation and packet segmentation
on transmit and checksum verification on receive.
The on-chip DDR SDRAM memory controller supports 32-bit or 64-bit interfaces with optional 8-bit ECC for
DDR devices from DDR200 to DDR333 with a peak data rate of 2.6 Gbps.
I2O messaging unit for communication between the 440 core and the PCI-X.
The 256-KB SRAM in the 440GX can be very useful in base stations for applications such as an L2 cache or as
local storage for fast access to tables, packets, or code.
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Revision 1.01 – September 7, 2004
440GP – Enterprise Ethernet Switch/Routers
using PowerPC Processors
Preliminary Application Note
Figure 2. AMCC PowerPC 440GX Embedded Processor Block Diagram
Arbiter
Arbiter
Up to 166 MHz
L2/SRAM Control
OPB
Bridge
Processor Local Bus (PLB)
256 KB
SRAM
PLB Perf
Monitor
128-Bit
DMA
Controller
Up to 83 MHz
32 K
D-Cache
w/ parity
MMU
w/ parity
Timers
MAL
JTAG
Trace
PowerPC 440 Core
On-Chip Peripheral Bus (OPB)
PCI-X
Bridge
32 KB
I-Cache
w/ parity
I2O
Messaging
Unit
DDR
SDRAM
Controller
UIC
TCP/IP
Accel.
Jumbo
Frame
RAM/ROM
Peripheral
Controller
Ext. Bus
Master
Controller
IIC
UART
GPIO
GPT
10/100
Ethernet
MAC
10/100/1 G
Ethernet
MAC
The IBM PowerPC 750FX microprocessor (see Figure 3) supports frequencies from 600 MHz to 1.0 GHz with 2.32
Dhrystone MIPS per MHz. The PowerPC 750FX has a 32-KB data cache and 32-KB instruction cache, each of
which is 8-way set associative and an on-chip 512-KB L2 cache with ECC that is 2-way set associative. The 60x
processor bus can operate at speeds up to 200 MHz.
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AMCC Confidential and Proprietary
Revision 1.01 – September 7, 2004
440GP – Enterprise Ethernet Switch/Routers
using PowerPC Processors
Preliminary Application Note
Figure 3. IBM PowerPC 750FX Embedded Microprocessor
Completion
Instruction
Fetch
System
Unit
Dispatch
Unit
GPR
FXU
1
FXU
2
Renames
32 KB
D-Cache
L2
Tags
32 KB
I-Cache
Branch
Unit
Load
Store
Unit
FPR
FPU
Renames
L2 Interface
w/ ECC
60x
BIU
512 KB L2 Cache
The IBM PowerPC 750CXe microprocessor has the same architecture as the 750FX with the following changes:
•
•
•
750Cxe supports frequencies from 400 to 700 MHz.
The on-chip L2 cache is 256 KB with ECC and is 2-way set associative.
The 60x processor bus operates at speeds from 100 to 133 MHz.
Both the 750FX and 750CXe may be used with the Discovery II system controllers from Marvell. This family of system controllers includes three parts: MV64360, MV64361, and MV64362 (shown in Figure 4).
The Marvell Discovery II MV64360 includes:
•
•
•
•
•
•
•
An on-chip 72-bit (64-bit with 8-bit ECC) DDR SDRAM memory controller with a 183-MHz clock rate (366Mbps data rate)
An on-chip 2-MB SRAM, two 64-bit 66-MHz PCI / 133-MHz PCI-X interfaces
A PCI bridge and arbiter
Three 10/100/1000 Mbps Ethernet MACs
Two multi-protocol serial channels
A two wire serial interface
Interrupt controllers
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Revision 1.01 – September 7, 2004
440GP – Enterprise Ethernet Switch/Routers
using PowerPC Processors
Preliminary Application Note
Figure 4. Marvell Discovery II System Controller Family
IBM PowerPC
750FX or 750CXe
Marvell
Discovery II
MV64360
55
55Mbps
64-bit
133MHz
MPSC 0
CPU Bus I/F
MPSC 1
2Mb SRAM
MII / GMII / TBI
10/100/1000
MAC
MII / GMII / TBI
10/100/1000
MAC
MII / GMII / TBI
10/100/1000
MAC
Cr
Fabric
72-bit
(64-bit with 8-bit ECC)
DDR SDRAM
Controller
183MHz Clock
Peripheral
Bus I/F
32
GPIO
32 pins
PCI-X 1
PCI-X 0
32/64-bit
66/133MHz
32/64-bit
66/133MHz
IBM PowerPC
750FX or 750CXe
Marvell
Discovery II
MV64361
55Mbps
MPSC 0
64-bit
133MHz
CPU Bus I/F
2Mb SRAM
55
MII / GMII / TBI
MPSC 1
MAC
Crossbar
Fabric
MAC
PCI-X 0
10
72-bit
(64-bit with 8-bit ECC)
DDR SDRAM
Controller
183MHz Clock
Peripheral
Bus I/F
32-bit,133MHz
32
GPIO
10
MII / GMII / TBI
PCI-X 1
32-bit
66/133MHz
32-bit
66/133MHz
IBM PowerPC
750FX or
Marvell
D
MV64362
55Mbps
55Mbps
MPSC 0
CPU Bus I/F
MPSC 1
10
MII / GMII / TBI
64-bit
133MHz
MAC
Crossbar
F
72-bit
(64-bit with 8-bit ECC)
DDR SDRAM
Controller
183MHz Clock
Peripheral
Bus I/F
32-bit,133MHz
GPIO
32 pins
PCI-X 0
32/64-bit
66/133MHz
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AMCC Confidential and Proprietary
440GP – Enterprise Ethernet Switch/Routers
using PowerPC Processors
Revision 1.01 – September 7, 2004
Preliminary Application Note
The Marvell Discovery II MV64361 also offers an on-chip 72-bit (64-bit with 8-bit ECC) DDR SDRAM memory controller with a 183-MHz clock rate (366-Mbps data rate) and an on-chip 2-Mb SRAM, but has:
•
•
•
•
•
•
Two 32-bit 66-MHz PCI / 133-MHz PCI-X interfaces
A PCI bridge and arbiter
Two 10/100/1000-Mbps Ethernet MACs
Two multi-protocol serial channels
A two wire serial interface
Interrupt controllers
The Marvell Discovery II MV64362 includes:
•
•
•
•
•
•
An on-chip 72-bit (64-bit with 8-bit ECC) DDR SDRAM memory controller with a 183-MHz clock rate (366Mbps data rate) with one 64-bit 66-MHz PCI / 133-MHz PCI-X interface
A PCI bridge and arbiter
One 10/100/1000-Mbps Ethernet MAC
Two multi-protocol serial channels
A two wire serial interface
Interrupt controllers.
See the Marvell Web site at http://www.marvell.com for more information on the Marvell Discovery II system controllers, the Marvell Prestera family of switching products, the Marvell product line of Ethernet transceivers, and the
Marvell production kits with Radlan OpENS networking software.
CATEGORIES/TYPES OF ENTERPRISE ETHERNET SWITCHES
Enterprise Ethernet switches fall into three main categories:
•
•
•
Desktop/workgroup switches
Stackable switches
Chassis-based/modular switches
Desktop/workgroup switches are often categorized by fixed function hardware platforms with little to no expansion.
Switches in this category are frequently packaged in thin, one unit high (1U) form factors and are called “Pizza-box”
switches, because their 1U form factor resembles a pizza box. These switches are usually interconnected using
some higher speed ports, that are referred to as “uplinks”. Desktop/workgroup switches can range from completely
unmanaged systems and lightly managed systems – which only provide a command line interface or web
support – to fully managed systems with network management system support via simple network management
protocol (SNMP). The fully managed switches maintain the required statistics/counters, called the management
information base, for each supported function.
Stackable switches are categorized by the presence of a high-bandwidth stacking connector that makes interconnecting several switches into a “stack” relatively easy. In some brands, one of the switches in the stack performs
the management for the other switches in the stack. This category of switches is usually fully managed and sometimes supports Layer 3 switching.
Chassis switches are categorized by their modularity. These switches have several “slots” that can be populated
with many different types of line cards. They usually have redundant features, are fully managed, often support
Layer 3/4, and are at the high end of the switch family.
An overview of the different categories and types of enterprise Ethernet switches is shown in Figure 5.
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440GP – Enterprise Ethernet Switch/Routers
using PowerPC Processors
Revision 1.01 – September 7, 2004
Preliminary Application Note
Figure 5. Categories and Types of Enterprise Ethernet Switches
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AMCC Confidential and Proprietary
440GP – Enterprise Ethernet Switch/Routers
using PowerPC Processors
Revision 1.01 – September 7, 2004
Preliminary Application Note
ENTERPRISE ETHERNET SWITCH/ROUTER IMPLEMENTATIONS USING IBM POWERPC
PROCESSORS
Today’s switches are usually constructed from:
•
•
•
•
A switching ASIC or ASSP with the desired level of hardware function
The Ethernet PHY parts that are required to support all of the Ethernet ports on the ASIC/ASSP
Any external packet and/or table memory required by the ASIC/ASSP
The control plane processor and its required memory
There are multiple ways to attach the control plane processor to the switching ASIC or ASSP. The best method
depends on the capabilities of the two parts and the required performance of the particular application. Two of the
primary methods of connecting the control plane processor to the switching ASIC/ASSP are to use one or more
Ethernet ports or a PCI/PCI-X interface.
The performance required by the control plane processor varies with the total bandwidth of the switch and the
amount of function provided by the ASIC/ASSP. Additional control plane processing power can be added to supplement functions that are weak or missing in the ASIC. For example, you could add a 440GX via 1-GB Ethernet to an
ASIC that does not support multicast in order to add multicast support via software. For examples of managed,
stackable, Ethernet switch chips, look at the Marvell Prestera-EX and Prestera-MX families of Ethernet switches at
http://www.marvell.com.
Some example implementations of enterprise Ethernet switches using IBM PowerPC processors are shown in Figure 6. The first switch is a managed desktop/workgroup switch with 24 10/100-Mbps Ethernet ports, two 10/100/
1000-Mbps uplink ports, and a 440GP control plane processor connected by PCI/PCI-X or by 10/100 Mbps Ethernet. The second example switch is a managed stackable switch with 48 10/100-Mbps Ethernet ports, four 10/100/
1000-Mbps uplink ports, a high bandwidth stacking port, and a 440GX control plane processor attached by PCI/
PCI-X or 1-Gbps Ethernet. Finally, the third switch is a managed desktop/workgroup switch with 24x10/100/1000Mbps Ethernet ports. This switch has a 750FX control plane processor attached via a Marvell Discovery II system
controller using either 1-Gbps Ethernet or PCI/PCI-X.
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Revision 1.01 – September 7, 2004
440GP – Enterprise Ethernet Switch/Routers
using PowerPC Processors
Preliminary Application Note
Figure 6. Enterprise Ethernet Managed L2/L3 Switch/Router Block Diagrams
PowerPC
440GP
Ethernet
Switch
Chip
10/100
Ethernet
or
PC/PCI-X
RGMII
Dual
10/100/1000
PHY
2 x 10/100/1000 Ethernet
RMII
SMII
Octal
10/100
PHY
Octal
10/100
PHY
Octal
10/100
PHY
Octal
10/100
PHY
24 X 10/100 Ethernet
Stacking
Uplink
PowerPC
440GX
10/100/1000
Ethernet
or
PC/PCI-X
Ethernet
Switch
Chip
RGMII
Dual
10/100/1000
PHY
4 x 10/100/1000 Ethernet
RMII
SMII
Octal
10/100
PHY
Octal
10/100
PHY
Octal
10/100
PHY
Octal
10/100
PHY
Octal
10/100
PHY
Octal
10/100
PHY
Octal
10/100/1000
PHY
Octal
10/100/1000
PHY
48 X 10/100 Ethernet
PowerPC
750FX
Marvell
Discovery II
Stacking
Uplink
10/100/1000
Ethernet
or
PC/PCI-X
Ethernet
Switch
Chip
RGMII
Octal
10/100/1000
PHY
Octal
10/100/1000
PHY
Octal
10/100/1000
PHY
Octal
10/100/1000
PHY
24 X 10/100/1000 Ethernet
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AMCC Confidential and Proprietary
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440GP – Enterprise Ethernet Switch/Routers
using PowerPC Processors
Preliminary Application Note
OVERVIEW OF ENTERPRISE ETHERNET SWITCHING SOFTWARE FROM LVL7
LVL7 Systems, Inc. (LVL7) has a comprehensive line of Ethernet switch software that is targeted at the enterprise
market. LVL7 focuses on switches ranging from the Layer 2 managed desktop switch to mid-range managed stackable switches and on to high-end chassis systems with Layer 3/4 functionality such as Quality of Service (QoS)
and Multicast.
LVL7 offers a base Layer 2 Ethernet switching software package with network management called the FASTPATH
Switching Software Suite. The network management support includes a command line interface, a Java™ enabled
Web interface, and SNMP v1/v2c/v3 support. Layer 3 IP routing can be added via the FASTPATH Routing Software
Suite. This package provides Layer 3 routing algorithms such as RIPv1, RIPv2, OSPFv2, and VRRP and also adds
VLAN routing support. For routing between autonomous systems, LVL7 offers the FASTPATH BGP-4 package as
an addition to the routing suite. The FASTPATH Multicast Software Suite is used to extend the routing suite by providing dynamic multicast IP routing capabilities using IGMPv2, DVMRP, PIM-SM, and PIM-DM. The FASTPATH
Quality of Service Software Suite can be added to provide QoS functions using diffserv, access control lists, and
bandwidth provisioning.
A diagram of how the LVL7 FASTPATH software suites apply to the types of enterprise Ethernet switches is shown
in Figure 7.
Figure 7. Suite of Enterprise Ethernet Software Packages from LVL7
FASTPATH
Software Suite
Switching
Layer 2
Unmanaged
Layer 2
Managed
Layer 2
Fully
Managed
Layer 3
Layer 3/4
Multprotocol
Multiservice
*
Management
Routing
QoS
Multicas
* Switching performed in hardware, no advanced software requirements
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440GP – Enterprise Ethernet Switch/Routers
using PowerPC Processors
Preliminary Application Note
All of the LVL7 software is portable across several families of ASIC, ASSP, and NP switches using the HAPI hardware abstraction layer. The software can also be ported to new ASICs or new families of switch hardware using the
example LVL7 Master Driver component as a reference. The LVL7 software is also portable across various operating systems using its OSAPI abstraction layer. LVL7 currently supports the software on the Linux and Wind River
VxWorks operating systems.
A diagram of the LVL7 FASTPATH software architecture is shown in Figure 8 below.
Figure 8. LVL7 FASTPATH Software Architecture for Enterprise Ethernet Switches
V
X
W
O
R
K
S
®
L
I
N
U
X
®
P
R
O
P
R
I
E
T
A
R
Y
Manageme
Serial
O
T
H
E
R
Enterpri
MIBs
Java
Applet
Telnet
System Intf
Mgr
Stat
Manager
BSP
Applications
3rd Party
RTOS
USMDB
S
Y
S
T
E
M
Configurator
Buffer Pool
Manager
HW Specific
RMON
OSAPI
Network
Intf Mgr
SNMP v1/ v2c/ v3
HTTP Server
CLI
Standard
MIBs
Architecture
S
U
P
P
O
R
T
Routing
Switching
GARP
GVRP
GMRP
802.1X
Port
Authent.
RADI
Client
BGP-4
BootP /
DHCP
Re
Route
Reflection
IGMP
Snooping
Static
MAC
Filtering
Port
Mirroring
Protocol
VLANs
OSPFv2
VRRP
Route
Flap
Damping
802.3ad
802.1D/
W/S
RIP
v1/v2
Router
Discovery
BGP-4
VLAN
Routing
Multicast
Qo
PIM-SM
DiffServ
PIM-DM
Access
Control Lists
DVMRP
Customer
Added
Function
Bandwidth
Provi
IGMPv2
DTL (Device Transformation Layer)
ANDL (Advanced Networking Device Layer) ist
HAPI – AMCC
nPSoft
Log
Manager
HAPI –
Broadcom
Strata & XGS
HAPI – Intel
Media Switch
HAPI –
Marvell
Prestera
HAPI –
SwitchCore
HAPI –
MasterDriver™
uCode – nPSoft
See the LVL7 Web site at http://www.lvl7.com/ or contact an LVL7 representative for more information on LVL7’s
line of FASTPATH software products for the Ethernet switch marketplace.
CONCLUSION
The scalability, compatibility, and variety of high-speed interfaces available make the AMCC PowerPC microprocessors ideal for control plane applications on a wide range of Ethernet switch designs. In addition, the broad array
of operating system software and application software available for the AMCC PowerPC microprocessors can
decrease the overall development/support expense, while also decreasing the time to market and time to revenue.
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using PowerPC Processors
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Preliminary Application Note
Applied Micro Circuits Corporation
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Phone: (858) 450-9333 — (800) 755-2622 — Fax: (858) 450-9885
http://www.amcc.com
AMCC reserves the right to make changes to its products, its datasheets, or related documentation, without notice and warrants its products solely pursuant to its terms and conditions of sale, only to substantially comply with the latest available
datasheet. Please consult AMCC’s Term and Conditions of Sale for its warranties and other terms, conditions and limitations.
AMCC may discontinue any semiconductor product or service without notice, and advises its customers to obtain the latest
version of relevant information to verify, before placing orders, that the information is current. AMCC does not assume any liability arising out of the application or use of any product or circuit described herein, neither does it convey any license under
its patent rights nor the rights of others. AMCC reserves the right to ship devices of higher grade in place of those of lower
grade.
AMCC SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED, OR WARRANTED TO BE
SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR OTHER CRITICAL
APPLICATIONS.
AMCC is a registered Trademark of Applied Micro Circuits Corporation. Copyright © 2004 Applied Micro Circuits Corporation.
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