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Proceedings of the Third International Conference on Modeling, Simulation and Applied Optimization
Sharjah,U.A.E January 20-22 2009
EMERGENCE OF OPTIMIZED COMMUNICATION IN SIMULATION OF
EHW MODULES
Yasser Baleghi Damavandi
Karim Mohammadi
Iran University of Science & Technology
Department of Electrical Engineering
P.O.Box 16846, Tehran, Iran
yasser [email protected]
Iran University of Science & Technology
Department of Electrical Engineering
P.O.Box 16846, Tehran, Iran
[email protected]
Based on the mentioned encouraging start with simple serial
adders, the present paper reports a real world function to
demonstrate potentials of this self organized communication.
ABSTRACT
Evolvable Hardware (EHW) is a new concept that aims the
application of evolutionary algorithms to hardware design. EHW
can adapt itself to unknown environment based on features of the
reconfigurable hardware.
Based on Evolvable Hardware features, a previous work reported
emergence of self organized communication between EHW
modules with simple function of a serial adder.
In the present paper EHW modules are to build up a self
organized communication to function as a frame grabber
peripheral card and a part of mainboard in the computer.
Watermarked video stream is used for ease of evaluation. The
results show a good convergence in common protocol and
simultaneous fault tolerance.
1.
A frame grabber card which interfaces a video stream to the
computer is assumed to contain an EHW module while the
motherboard contains the same raw module to receive the video
data.
Since genetic algorithm as the optimization engine of EHW
needs a fitness function, a very good way of output video
assessment is utilized here which is described in section 2. This
section also includes a detailed description to overall system that
is simulated in this experiment. Section 3 will illustrate some
important results of the simulation while the paper concludes and
poses the future work in section 4.
2.
INTRODUCTION
Evolvable Hardware (EHW) is a technique that has led to some
radical new designs for analog & digital circuits [1,2,3]. EHW
applies special algorithms called Evolutionary Algorithms (EA)
to hardware design that consists of programmable elements. In
EHW, a researcher specifies the desired output from the system
and then the "EA" evolves a circuit on the programmable device
that gives the desired output.
While simulating EHW agents for an evolutionary
communication the question arises that: "Under what conditions
could these agents build up a self organized communication?”
This question is well answered by Gmytrasiewicz et al [4]. The
requirements for such a communication are: possessing a
Knowledge Representation Language (KRL), purposefulness and
rationality for the involved agents. Briefly, all of these
requirements can be guaranteed by using the evolutionary
algorithm in EHW modules as communicating agents.
SETTING THE STAGE
Figure 1 shows the system diagram to simulate the EHW modules
communicating to each other to receive and monitor a
watermarked video stream.
Clock
Watermarked
Video Stream
To prove this, the authors had reported the emergence of coevolutionary communication between EHW modules in [5]. The
mentioned modules were to evolve to an 8 bit serial adder.
This kind of communication was shown to be highly fault
tolerant, especially to the permanent physical faults in
communication lines [6].
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EHW1
Receive &
Encode
Fitness
EHW2
D0-D7
Decode &
Monitor
Video Data
To Monitor
Key
Recovery
Fitness
Key Evaluator
Figure 1. System Diagram of EHW-based frame grabber
Proceedings of the Third International Conference on Modeling, Simulation and Applied Optimization
Sharjah,U.A.E January 20-22 2009
Cb Signal
Y Signal
Cr Signal
Figure 2. Interface signals produced by EHW1 to transmit the first 20 pixels of first line
2.1. Watermarked Video Stream
A constant key is watermarked in every frame of the video
stream. This method is based on digital watermark technology.
Invisible reference information (watermarked key) is embedded
into the video sequence, which may be corrupted during
transmission and can be retrieved from the decoded video at the
destination key evaluator. By the comparison of retrieved
watermark with the original watermark stored in the destination,
we are able to assess how much video sequence quality degrades
during the transmission, so as to achieve our goal to assess the
video quality without reference [7].
first 20 pixels of first line of image that is transferred by EHW1.
As illustrated, this process needs 52 pixel clocks i.e. 1.6 times
redundancy in comparison with the original data. This
redundancy however is time consuming here but as you will see
in section 3.3 it would be useful for fault tolerance, other than this
protocol was emerged automatically which is valuable itself!
Finally after 107 generations the video stream was successfully
transmitted and monitored at the destination. An example of
transmitted image is shown in figure 3. This figure shows the
correct retrieval after the evolution time.
The evaluator will monitor recovered key from video data and
will return its hamming distance from the predetermined original
key. This value will be supposed as the fitness value in genetic
algorithm which determines the new configuration of EHW
modules. Using the mentioned fitness function, each of the EHWs
has to adapt, to score the best, in an evolutionary process. The
key recovery process assures that video data has been recovered
successfully. This way has been used for no-reference video
quality assessment.
The D0-D7 interface signals as shown in figure 2 will be
generated by EHW1 and interpreted by EHW2 that can represent
an emerging common language between the two modules. The
input image has 320x240 pixels per frame. Figure 2 shows the
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EHWbased
system
Figure 3. Input and output images examples, produced by
Matlab Image acquisition toolbox
Proceedings of the Third International Conference on Modeling, Simulation and Applied Optimization
Sharjah,U.A.E January 20-22 2009
point crossover and mutation operators with Gaussian function,
tournament selection mechanism and forward migration.
2.2. EHW1
As shown in figure 3, the input image is captured by the image
acquisition toolbox of Matlab 7.5 software. The stream format is
in YCbCr color space which has three 8-bit parameters to
represent each pixel [8]. Thus there are 24 lines as input to EHW1
and the same number of lines are output from it. A truth table that
describes such a logic system needs: 224x24=402,653,184 bits of
chromosome for genetic algorithm that looks to be very immense!
A way to reduce this chromosome is to divide the unrelated bits
and use individual EHW modules to encode each of them. That is
why the EHW1 consists of 3 independent truth table modules,
each one with 8 inputs and 8 outputs. This results in 28x8=2048
bits for each module that shows a good reduction even when
taking account all three modules i.e. 6,144 bits.
The above mentioned structure, in an evolutionary process,
produces the signals of figure 2. The whole communication signal
data is used in an emerged language assessment analysis in
section 3.1.
It is obvious from the nature of the problem, that the goal
architecture of EHW modules is a sequential digital circuit. For
an appropriate genotype, we used one of the standard forms of a
sequential circuits (shown in Figure 4), in which, it is made up of
an n bit register, and a combinational circuit that provides the
feedbacks and outputs [9].
3.
Results
Evolution of EHW modules with the mentioned properties has
resulted in three emergent behaviors in this experiment. These
emergent behaviors are considered as follows:
3.1. Emergence of a communication in large scale
hardware
In this simulation the system resulted in 100% key recovery. This
means that the raw hardware modules of EHW1 & EHW2 could
establish a self organized communication without any
predesigned protocol. The genetic algorithm that was used for
this simulation guaranteed an optimized language with very good
parameters. As stated in [10] a language can be emerged based on
evolution of signals. So the interface signals can refer to a
language and this language can even be evaluated.
One of the language evaluation parameters is lexicon entropy
[11]. The lexicon entropy for any concept (video data) is a
function of lexicons (D0-D7) that simultaneously refers to it and is
derived from equation 1.
H(X) =
1
∑ P(x) × log( P(x) )
(1)
x∈ X
Register
.
.
.
In equation 1, H(x) is the lexicon entropy of the random variable
x and P(x) is the probability of x (lexicon) for conveying a
concept. Therefore if only one word (D0-D7) refers to a concept
(desired status) the entropy approaches 0. This has happened for
the mentioned simulation in 107 generations. Figure 5 shows the
evolution of generations until they gain the best (near zero)
fitness.
Combinational
Circuit
Fig.4 Representation of a sequential circuit
Using fig 4, we only need to evolve the combinational circuit, for
which, the truth table is used. The outputs columns of the truth
table of the combinational circuit are used as the chromosome
chain (the input columns are implicit) and a register is roughly
selected as a fixed parameter.
2.3. EHW2
EHW2 has the same raw architecture of EHW1 and is to coevolve with it to reach the fitness of decoding the video. The
evaluation process takes place after the output of EHW2 is ready
and the original key is compared with the retrieved watermarked
data.
The genetic algorithm used for this process had the following
parameters: 30 random individuals for initial population, two-
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Figure 5. Genetic algorithm process for EHW modules
Proceedings of the Third International Conference on Modeling, Simulation and Applied Optimization
Sharjah,U.A.E January 20-22 2009
Y Signal
Cb Signal
Cr Signal
Figure 6. Interface signals encountering s_a_0 and s_a_1 faults
As stated in section 2.1 in the evolved protocol there is a
redundant data of 1.6 times for conveying a color concept.
encoder which adds redundancy and transmits it to the decoder.
The decoder is able to retrieve the video data.
3.2. Automatic Hardware Design
In this process two hardware modules have been automatically
designed (evolved). The hardware here means the VHDL code of
the EHW, which describes the EHW module. This description is
derived from the genome i.e. the truth table and the
predetermined architecture. For this purpose the Simulink,
Genetic Algorithm and direct search and Link for ModelSim®
toolboxes of Matlab7.5 are utilized in cooperation with the
Modelsim software in this experiment. Transferring from truth
table to a hardware description is done by Link for Modelsim
toolbox of Matlab and inspired by architecture of a PLD which is
depicted in figure 7.
Figure 7. PLD architecture for description of the evolved
hardware
3.3. Fault Tolerant Protocol
The genome that described the hardware and was used in genetic
algorithm is well described in [5]. This hardware contains an
In this subsection the idea of fault tolerance in EHW modules
communication is put to test. For this purpose the previously
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Proceedings of the Third International Conference on Modeling, Simulation and Applied Optimization
Sharjah,U.A.E January 20-22 2009
described model will face different types of faults in the
communication lines. As the EHW modules are two electronic
boards that communicate with each other via a connector, the fault
model can contain related cases. A typical fault affecting the
mentioned connections is a short between a pin and the power
supply line in the connector. Considering the type of these pins,
one of the following logical faults may happen.
RS232, RS485, USB, I2C ,… which undoubtedly will lead to a
failure.
Stuck at 1/0: A short between ground or power and the signal line
can make the signal remain at a fixed voltage level. The
corresponding logical fault consists of the signal being stuck at a
fixed logic value v (v ε {1,0}) , and it is denoted by s-a-v. Since
there are some power and usually more ground pins in such a
connection, a short between them and the signal lines will cause sa-1/0 faults and thus they are put in the fault model.
Another remarkable property is that there is no need to follow the
classic fault tolerant algorithms that contain fault detection,
location and recovery, respectively. For example in classic fault
detection a TPG is required, while the fault will be detected in the
fitness evaluation process of EHW modules in this work.
In many cases, the effect of an open on a signal line with only one
fan-out is to make the input that has become unconnected due to
the open, assume a constant logic value and hence appear as a
stuck fault [12]. Supposing a shielded, low length connection
which brings about negligible radiation noise and delay faults, the
introduced model can cover many kinds of physical faults that
may happen in the EHW communication line.
The main advantage of this system is gaining an intrinsic fault
tolerance. The varying nature of EHW gives it an intrinsic fault
tolerance [6]. Whenever a fault happens at communication lines
that damages the video data, the key cannot be recovered
correctly and it will lead to a degradation of the fitness. This will
result in a change in genome and consequently hardware. The
evolutionary loop will continue until it reaches the best fitness i.e.
the key and video data are recovered correctly. The video and D0D7 signals in faulty condition are depicted in figure 6 as an
example of an s-a-0 in Y line and s-a-1 in Cb and Cr lines all
happened on D0 line.
When D0 experience a stuck at 0/1 fault (shorts to GND/Vsupply)
the system will try to transfer the data without D0 line. This may
be more time-consuming but what is gained instead of the time
drawback is a correct function under faulty condition.
Comparing this varying protocol, it seems to be a very good
option when human intervention is not possible at faulty
condition like the space applications. That may be the property of
evolvable hardware that has attracted the attention of NASA [13].
What is tested here is Single Stuck Fault, (SSF) that means only
one line is faulty during the simulation. Another term is Multiple
Stuck Fault (MSF) which refers to more than one faulty line
during the communication. This will be considered in future
work.
Another task from the list of future work is a full duplex
communication. In this experiment one module was supposed as
a sender and another one was determined as a receiver. A
development can be a simultaneous role of sender/receiver for
both EHW modules.
Physical layer characteristics like voltage level and clock
frequencies are supposed to be fixed in this experiment, but
utilizing FPAA like some referenced EHW applications [14] will
give another dimension of flexibility to this kind of
communication.
The evolved protocol is a point to point one, which can be
developed to be a bus one too.
Finally we are hopeful that these researches pave the way for
future adaptive hardware agents that no more need a common
protocol, and can be leaved to make improvements, modifications
and tolerate faults.
Comparing figure 6 with figure 2 shows that a new protocol is
evolved while encountering the fault and this can be taken into
account. The signals are again for conveying 20 pixel colors but
with more pixel clocks i.e. 80.
In the Single Stuck Fault (SSF) simulations performed here, all
combinations of D0…D7 from YCbCr channels are put to test and
the results showed an insensitivity of the system to fault
occurrence in 4th line of Cb! It shows a redundancy in this
protocol (1.6 times) that made line 4 insensitive of fault. The
same behavior is reported in EHW-based robot controllers [12].
4.
Conclusion and Future Work
Most of the communication protocols in computer peripheral
devices are not immune against the permanent faults that may
happen in the communication channel. For example one can
assume a stuck at 1 fault in one of the communication lines of
5.
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Sharjah,U.A.E January 20-22 2009
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