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EKT422 Computer Architecture [ William Stallings Book ] ( Note: THREE (3) Students per Batch to prepare the soft copy ) Unit 1 Organization of CPU, IAS Computer structure and memory format, Instruction types and times, Instruction cycle events, Fundamental computer elements, Moore’s law, PDP bus, Intel evolution, DRAM use, Peripheral technologies, Pentium versus PowerPC. pp.1 to pp.46 Chapters 1 and 2 Specific pages 6,11,18,19,21,23,27,28,30,33,35,36,40,41,42,43 ( Weeks 1 and 2 ) 2 (TWO) Batches Unit 2 Top-Level view, CPU Registers, Interrupt classes, memory and I/O module, Elements of bus design, Peripheral component interconnect, Timing diagrams, memory characteristics, cache memory principles, Direct/Set Associative mapping, multilevel caches, Pentium 4, PowerPC Cache organization, pp.47 to 136 Chapters 3 and 4 Specific pages 52,53,58,68,74,79,80,81,84,86,88,97,103,104,105,106,107,109,113,119,120,123, 124,125 ( Weeks 2, 3 and 4 ) 3 (THREE) Batches Internal memory, dynamic/static RAM, ROM types, Chip Packaging, Error Correction, synchronous DRAM, RDRAM, Cache DRAM 2-in-1 pp.137 to 162 Chapter 5 Specific pages 140,141,149,151,155,156 (Week 4) 2 (TWO) Batches External memory - disk organization, RAID levels, compact disk CD optical memories, DVDs, Tapes, speed comparism of the secondary memories pp.163 to 194 Chapter 6 Specific pages 169,171,172,173,174,176,184,189,190 (Weeks 4 and 5) 2 (TWO) Batches I/O devices, Keyboard/Monitor, data rates of typical I/O, data transfer schemes, 8255 PPI, cycle stealing data transfer, I/O channel, parallel/serial I/O buses, transceiver pp.195 to 236 Chapter 7 Specific pages 198,201,202,203,204,205,207,216,217,218,219,223,224,225,226,233 (Weeks 5 and 6) 2 (TWO) Batches Unit 3 Types of operating systems, operating system services, Kernel, scheduling types, memory management, demand paging, translation lookaside buffer, Segmentation,memory management hardware of Intel processors pp.237 to 280 Chapter 8 Specific pages 238,239,240,248,250,251,252,253,256,257,261,263,265,266,267,268,277,278 (Weeks 6 and 7) 2 (TWO) Batches Computer Arithmetic and fault tolerance pp.283 to 328 Chapter 9 Specific pages 284,285,288,297,298,300,301,302,303,304,307,308,309,312,313,315,324,325 (Week 7) 2 (TWO) Batches Unit 4 Instruction sets, types of operands, size of operands, Instruction types, procedure calls, Pentium operation types, assembly language pp.329 to 380 Chapter 10 Specific pages 332,339,341,342,343,356,357,364,365,366,367 (Weeks 7 and 8) 3 (THREE) Batches Addressing modes, effective address, Pentium ways of addressing, allocation of bits, variable length instructions, PDP 11 instruction formats, Pentium and PowerPC instruction formats pp.381 to 410 Chapter 11 Specific pages 381,382,390,391,392,393,396,397,400,401,404,405,406,407,408,409,410 (Weeks 8 and 9) 2 (TWO) Batches Unit 5 CPU structure and function, RISC/CISC compute structures, Internal CPU structure, register organization, Data Flow cycles, pipelining, pipeline performance, conditional branches, loop buffer and branch prediction, delayed branch, The Pentium processor, system interrupt routines, The Power PC approach, Reduced instruction set computers, register file versus cache, compiler-based register optimization, characteristics of RISC, pipelining issues, MIPS R4000 organization, scalable processor architecture, RISC versus CISC, instruction level parallelism and dependencies, design issues and branch prediction, Pentium 4 POWER PC RISC-based approach, more functional units, super scalar versus vectorization conflicts Chapter 12 pp.411 to 460 (Weeks 9 and 10) 3 (THREE) Batches Chapter 13 pp.461 to 504 (Weeks 10 and 11) 3 (THREE) Batches Chapter 14 pp.505 to 540 (Weeks 11 and 12) 3 (THREE) Batches Unit 6 Parallel processing, Flynn’s taxonomy, SIMD, MIMD, multiprocessing and networks, symmetric multiprocessors, shared caches, coherence problem and solutions, The MESI protocol, nodes and clusters, operating system design issues, SMP versus clusters, memory access configurations, pipelined ALU and vector processes, View conclusions pp.641 to 692 Chapter 18 (Weeks 13 and 14) 3 (THREE) Batches Chapter 17 pp.599 to 640 Microprogrammed Control 3 (THREE) Batches