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Slide 18
transitie = overgang
Slide 29
One's complement is een van de twee getalsrepresentaties die in computers algemeen in omloop zijn.
Positieve getallen worden daarin weliswaar voorgesteld door een bitrij beginnend met een 0 en negatieve beginnend met een 1,
maar het tegengestelde van een getal bestaat uit de bitrij met alle bits geïnverteerd, dus de rij met complementaire bits. Het
positieve getal 79 bijvoorbeeld wordt (met 8 bits) voorgesteld door 0|1001111 en -79 door 1|0110000. Men kan de voorstelling
van -79 verkrijgen door de bitrij van 79 af te trekken van de rij met alleen enen: 11111111. Hiervan komt de naam: one's
complement. Deze representatie kent twee bitrijen die 0 voorstellen: 00000000 en 11111111.
(79)D=(1001111)B
(127)D = (0|1111111)B, (-128)D = (1|0000000)B. (0)D = (0|0000000)B
Slide 30
Two’s Complement: Het positieve getal 79 bijvoorbeeld wordt (met 8 bits) voorgesteld door 0|1001111 en -79 door 1|0110001.
Tellen we beide op, dan krijgen we als som de rij 100000000, die overigens zelf in de representatie niet voorkomt. (127)D =
(0|1111111)B, (-128)D = (1|0000001)B. (-1)D = (1|1111111)B
Slide 36
vermijden van spikes: Bij de overgang tussen stand 7 en 8 wijzigen bij een gewogen-binair gecodeerde gever alle bits. Een
windvaan met 16 sectoren en 4-bits codering zal dan, als hij tussen code 7 en 8 staat te twijfelen, misschien een tussenstand
1111 of 0000 (of alle andere mogelijke codes!) kunnen geven, bij een Gray-code is er geen twijfel tussen 0100 en 1100 omdat
alleen het linker bit wijzigt.
Encoderschijven: Gray codes are used in position encoders (linear encoders and rotary encoders), in preference to
straightforward binary encoding. This avoids the possibility that, when several bits change in the binary representation of an
angle, a misread could result from some of the bits changing before others. Rotary encoders benefit from the cyclic nature of
Gray codes, because the first and last values of the sequence differ by only one bit (in slide 7=100 en 0/8=000 ipv van 7=111
en 0/8=000 (000=k*8 als k=0,1,2,3,…,n)).
Slide 63
"Large-Scale Integration" (LSI) ( mid 1970s) = tens of thousands of transistors per chip.
Een schottkydiode is een halfgeleiderdiode die bestaat uit een overgang tussen een metaal en een n-gedoteerde halfgeleider in
plaats van de gebruikelijke pn-overgang in een gewone halfgeleiderdiode.
De schottkydiode is genoemd naar de Duitse natuurkundige Walter Schottky. De gelijkrichtende werking van een dergelijke
overgang werd al in 1874 door Ferdinand Braun waargenomen.
Voordelen:
lagere voorwaartse spanningsval (voorwaartse spanningsval = de spanningsval over de diode als de stroom in doorlaatrichting
stroomt)
snel schakelgedrag
geringe warmteontwikkeling in diode
Nadelen:
doorgaans hogere kostprijs dan van gewone pn-dioden
de toegelaten inverse spanning van schottkydioden is beperkt. Het is daardoor moeilijk schottkydioden te vinden met een
toegelaten inverse spanning van meer dan 100 V
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Vroeger werden bij sommige digitale bouwstenen, uitgevoerd in TTL-technologie, schottkydioden ingebouwd in de geïntegreerde
schakeling om de schakelsnelheid van de bipolaire transistoren te vergroten.
Slide 64
Vermogensdissipatie = verdeling vermogen
Slide 71
Fan out
De fan out is het getal dat aanduidt met hoeveel ingangen, van een zelfde familie, één uitgang
mag belast worden.
Elke ingang die met een bepaalde uitgang wordt verbonden, vraagt een bepaalde stroom om
in zijn logische toestand terecht te komen.
Hoe meer ingangen er met de uitgang verbonden worden, hoe meer stroom de uitgang moet
leveren.
Indien beide delingen niet gelijk zijn aan elkaar, geldt het kleinste getal natuurlijk als fan out.
Let op dat u nooit de maximale stroom (IOH en IOL) overschrijdt. De logische niveau's worden
dan niet meer bereikt. Wordt de belasting op één uitgang te groot, dan kan u nog altijd een
belastingssplitsing doorvoeren over meerdere identieke functies.
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Sink & source: The terms refer to the direction of the current.
If it's sink, it is flowing into the output. Let's say NPN, emitter to gnd and a load between Vdd and Collector will SINK
If it's source, it is flowing out of the output. Let's say PNP, emitter to Vdd and a load between Gnd and Collector will Source.
Slide 72
In electronics, when describing a voltage or current step function, rise time refers to the time required for a signal to change
from a specified low value to a specified high value. Typically, these values are 10% and 90% of the step height. The output
signal of a system is characterized also by fall time: both parameters depend on rise and fall times of input signal and on the
characteristics of the system.
In electronics, fall time (pulse decay time) is the time required for the amplitude of a pulse to decrease (fall) from a specified
value (usually 90 percent of the peak value exclusive of overshoot or undershoot) to another specified value (usually 10 percent
of the peak value exclusive of overshoot or undershoot). Limits on undershoot and oscillation (aka, ringing or hunting) may need
to be specified when specifying fall time limits.
The transition time is the time a dynamical system needs to switch between two different stable states, when responding to a
stable input signal. In a logic circuit (a discrete-time dynamical system whose state is representable as a boolean-valued vector
function of time) undergoing a change of state, it identifies the rise time or the fall time of the output voltage. It is therefore
correct to speak of two types of transition times
: transition time Low-to-High. It is the rise time of a logic gate's output voltage
: transition time High-to-Low. It is the fall time of a logic gate's output voltage
Eerste tekening (Vin) geeft de rise en fall times weer
De tweede en derde tekening (Vin en Vuit) geven de vertragingstijden weer.
(Dit omdat het wat onduidelijk was).
Slide 75
Dissipatie
Onder dissipatie wordt verstaan de onvermijdelijke warmteontwikkeling in een belasting of regeling van elektrische
stroom. Vooral in halfgeleiders speelt dissipatie een grote rol: schakelelementen zoals triacs en thyristoren hebben altijd
een inwendige weerstand waarover een spanning valt als ze stroom geleiden. Ook regelelementen zoals transistoren
vertegenwoordigen een weerstand. Het vermogen wat daardoor wordt opgewekt wordt dissipatie of gedissipeerd
vermogen genoemd en zal de component verwarmen.
Bij toepassing van hoge frequenties speelt dissipatie ook een grote rol omdat hierbij capacitieve stromen mee gaan spelen en
omdat schakelverliezen optreden.
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Ook op andere gebieden van de techniek worden ingenieurs geconfronteerd met dissipatie. Deze term wordt overigens vooral
gebruikt als er gesproken wordt over de problematiek van het wegwerken van verliezen om te voorkomen dat de temperatuur
van een apparaat te hoog oploopt, kortom over koeling. De verliezen worden in dit verband veelal als onvermijdelijk beschouwd.
Zo is het rendement van stoommachines beperkt door natuurwetten (Carnot). In computers neemt de warmtedissipatie vaak toe
als de snelheid wordt verhoogd (en geen andere maatregelen worden genomen). Warmtedissipatie is ook een probleem bij het
ontwerp van satellieten, omdat die hun overtollige warmte slechts kwijt kunnen door straling en niet aan lucht of water kunnen
afgeven.
Slide 73
Some digital devices support a form of three-state logic on their outputs only. The three states are "0", "1", and "Z" (open circuit,
niet verbonden).
Commonly referred to as tristate [7] logic (a trademark of National Semiconductor), it comprises the usual true and false states,
with a third transparent high impedance state (or 'off-state') which effectively disconnects the logic output. This provides an
effective way to connect several logic outputs to a single input, where all but one are put into the high impedance state, allowing
the remaining output to operate in the normal binary sense. This is commonly used to connect banks of computer memory and
other similar devices to a common data bus; a large number of devices can communicate over the same channel simply by
ensuring only one is enabled at a time.
It is important to note that while outputs can have one of three states, inputs can only recognise two. Hence the kind of relations
shown in the table above do not occur. Although it could be argued that the high-impedance state is effectively an "unknown",
there is absolutely no provision in the vast majority of normal electronics to interpret a high-impedance state as a state in itself.
Inputs can only detect "0" and "1".
When a digital input is left disconnected (i.e., when it is given a high impedance signal), the digital value interpreted by the input
depends on the type of technology used. TTL technology will reliably default to a "1" state. On the other hand CMOS technology
will temporarily hold the previous state seen on that input (due to the capacitance of the gate input). Over time, leakage current
causes the CMOS input to drift in a random direction, possibly causing the input state to flip. Disconnected inputs on CMOS
devices can pick up noise, they can cause oscillation, the supply current may dramatically increase (crowbar power) or the
device may completely destroy itself.
Tri-state
Tri-state als schakelaar
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Tri-state (drie toestanden) is een aanduiding van een digitale uitgang die zich in drie verschillende toestanden kan bevinden,
namelijk hoog (logische 1), laag (logische 0) of zwevend (open cricuit, niet verbonden).
Dank zij tri-state is het mogelijk dat een bus in meerdere richtingen werkt. De databus van een computer, bijvoorbeeld,
transporteert gegevens van de processor naar het geheugen en andersom, hij kan zelfs dienen voor het uitwisselen van
gegevens tussen alle aangesloten apparaten. Op elk moment mag echter slechts een apparaat een lijn van de bus hoog of laag
maken. Alle andere apparaten mogen de lijn niet beïnvloeden, kunnen eventueel de lijn als ingang gebruiken.
Voor tri-state is het nodig dat wordt aangegeven welk apparaat de 'controle' van de bus heeft. Vaak gebeurt dat door het adres
van dat apparaat op de adresbus te zetten.
Slide 93
Minterm realisatie: Wanneer is uitgang 1 en hoe zorg ik er dan voor met AND (AND(A,B,C)=1)? Deze groepen verbinden met
OR en gelijkstellen aan Q.
BV.
Q=1 als A=0, B=1, C=1 => (!A)*B*C
Q=1 als A=1, B=1, C=1 => A*B*C
Voor de rest altijd Q=0.
Resultaat: Q=(!A)*B*C+A*B*C
Maxterm realisatie: Analoog als de minterm realisatie, maar men kijtk nu wanneer de uitgang 0 is. Hoe zorg ik ervoor dat alles 1
is met AND (AND(A,B,C)=1)? Elke groep inverteren en dan allemaal samenvoegen met AND en gelijkstellen aan Q.
BV.
Q=0 als A=0, B=1, C=1 => !A*B*C
Q=0 als A=1, B=1, C=1 => A*B*C
Voor de rest altijd Q=0.
Resultaat: Q=!((!A)*B*C)*!(A*B*C)
Slide 96
Overgang is gedaan met de 2e wet van De Morgan
Slide 99
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2-4 Decoder with Enable
Remember when we talked about memory chips. There was a chip-enable. If this control input was active, then either a read or
write was performed. If it was inactive, then neither read nor write is performed.
The enable control bit for the decoder acts somewhat like the chip enable.
Here's how the enable bit works:
Enable
Operation
e=0
All outputs are 0
e = 1 Acts like regular decoder without enable
If the enable is active, it behaves as a regular decoder. If it's not active, then all outputs are 0.
This is equivalent to the following condensed truth table.
x1 x0 z3 z2 z1 z0
0 0 0 0 0 e
0 1 0 0 e 0
1 0 0 e 0 0
1 0 e 0 0 0
Slide 100
00 (A1=0, A0=0 komt hier uit)
01 (A1=0, A0=0 komt hier uit)
…
Slide 101
(kijken naar datasheet van 138 decoder in de H/L tabel)
HHH=ABC=!Q7
HHL=AB!C=!Q6
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HLL=A!B!C=!Q4
LHH=!(A)BC=!Q3
Slide 109
A programmable logic device or PLD is an electronic component used to build reconfigurable digital circuits. Unlike a logic
gate, which has a fixed function, a PLD has an undefined function at the time of manufacture. Before the PLD can be used in a
circuit it must be programmed, that is, reconfigured.
Op de tekeningen ziet men kruisen staan, dit zijn keuzes die men kan make nom lijnen te verbinden. Programmable AND wil
zeggen dat me “kruisjes kan zetten” vooraf de AND poorten. Bij OR is dit analoog. Niet programmeerbare AND en
programmeerbare OR bijvoorbeeld houdt in: AND poorten -> kruisjes zetten (=PLD programmeren) -> OR poorten.
Slide 130
The objective is to cover all the 1's on the map in the fewest number of groups and to create the largest groups to do this.
Slide 142
Resultaat is een bloktandgolf waarbij elke tand 3 keer de propagatietijd van de invertor breed is. __|||||||||__|||||||||__||||||||__||||||||_
…
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Edge-Triggered Flip-flops
An edge-triggered flip-flop changes states either at the positive edge (rising edge) or at the negative edge (falling edge) of
the clock pulse on the control input. The three basic types are introduced here: S-R, J-K and D.
Click on one the following types of flip-flop. Then
its logic symbol will be shown on the left. Notice the
small triangle, called the dynamic input indicator, is
used to identify an edge-triggered flip-flop.
Positive edge-triggered (without bubble at Clock input):
S-R, J-K, and D.
Negative edge-triggered (with bubble at Clock input):
S-R, J-K, and D.
The S-R, J-K and D inputs are called synchronous inputs because data on these inputs are transferred to the flip-flop's
output only on the triggering edge of the clock pulse.On the other hand, the direct set (SET) and clear (CLR) inputs are
called asynchronous inputs, as they are inputs that affect the state of the flip-flop independent of the clock. For the
synchronous operations to work properly, these asynchronous inputs must both be kept LOW.
Edge-triggered S-R flip-flop
The basic operation is illustrated below, along with the truth table for this type of flip-flop. The operation and truth table
for a negative edge-triggered flip-flop are the same as those for a positive except that the falling edge of the clock pulse
is the triggering edge.
As S = 1, R = 0. Flip-flop SETS on the rising clock edge.
Note that the S and R inputs can be changed at any time when the clock input is LOW or HIGH (except for a very short
interval around the triggering transition of the clock) without affecting the output. This is illustrated in the timing diagram
below:
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Edge-triggered J-K flip-flop
The J-K flip-flop works very similar to S-R flip-flop. The only difference is that this flip-flop has NO invalid state. The
outputs toggle (change to the opposite state) when both J and K inputs are HIGH. The truth table is shown below.
Edge-triggered D flip-flop
The operations of a D flip-flop is much more simpler. It has only one input addition to the clock. It is very useful when a
single data bit (0 or 1) is to be stored. If there is a HIGH on the D input when a clock pulse is applied, the flip-flop SETs
and stores a 1. If there is a LOW on the D input when a clock pulse is applied, the flip-flop RESETs and stores a 0. The
truth table below summarize the operations of the positive edge-triggered D flip-flop. As before, the negative edgetriggered flip-flop works the same except that the falling edge of the clock pulse is the triggering edge.
Alle flipflop slides
Q+ is de waarde van Q na het doorlopen van de flipflop (na verandering)
Bv. Bij T
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T
Q
Q+
1
1
0
0
0
1
1
0
1
0
1
0
Slide 150
Dankzij de klok kunnen enkel de master OF de slave aanbeurt zijn en dus toggles veroorzaken. Omdat de uitgang verbonden is
met de slave en de feedback met de master kunnen deze nooit tegelijkertijd veranderen. Bv. Zolang J=1 en K=1 en C=1 kan de
Q niet veranderen en kan er dus max 1 keer getoggled worden. Deze toggle wordt doorgevoerd van zodra de slave actief wordt
(C=0), maar dan maakt het niet uit of J en K nog beiden gelijk zijn aan 1 want de 2 AND poorten bij J en K zijn zowiezo 0 door
C (en dus is er geen verandering). Dit bedoelt men met de 2 niveau’s die ervoor zorgen dat J en K voor een langere tijd hoog
mogen zijn.
Slide 156
Als ge Q3Q2Q1Q0 bekijkt bij elke wisseling van Q0, dan ziede dat het verloop analoog is met het optellen in een 4-bits getal
(0000, 0001, 0010, 0011, 0100, 0101,…). De JK flipflops zijn telkens negatief getriggerd, waardoor elke JK als een tweedeler
functioneert.
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Slide 168
D1
Q2
Q1
0
0
1
x
 D1=Q2
D2
Q2
Q1
1
0
0
x
 D2=!Q1*!Q2=!(Q1+Q2) (DeMorgan)
Slide 175
Q1 en Q0 zijn geheugens die de vorige STAAT onthouden, IN is de huidige input en D1 en D0 stellen de volgende STAAT
voor.
Dus Q1 en Q0 = A B C of D
In schema:
A
A
B
B
D
D
C
C
“ge hebt 4 verschillende staten 2 bits nodig
hier hebben ze gekozen voor: A = 00, B = 01 ... (ik ga ervan uit dat dit volledig willekeurig is)
Q1, Q0 en IN stellen alle mogelijke combinaties voor
Q1 en Q0 definieren de huidige staat
A A B B D D C C (van boven naar onder)
afhankelijk van uw IN waarde, volgt ge op uw statendiagram in welke staat ge uitkomt: bv. eerste regel in waardentabel: Q1 = 0,
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Q0 = 0 (dit is staat A); IN = 0, dus de volgende staat is terug A (zie statendiagram)
bij regel 6:
Q1 = 1
Q0 = 0
dit is staat D
als ge in staat D zit, en IN is 0, dan komt ge in staat A
is IN=1, dan komt ge terug in staat D
dus in die waardentabel moet ge niet zoeken/kijken naar 011 ofzo, want A, B, C en D zijn willekeurig gedefinieerd”
Slide 178
Schuifregister
Een digitaal schuifregister is een aaneenschakeling van D-flipflops waarbij de dataingang van een flipflop verbonden is met de
Q uitgang van de vorige flipflop in de keten. Alle kloklijnen van de flipflops zijn met elkaar verbonden. Een schuifregister schuift
bij elke klokpuls de gegevens in het register een positie op. Een bit dat aan de ingang ingeklokt wordt, verschijnt na X
klokpulsen weer aan de uitgang van het schuifregister, waarbij X het aantal flipflops is.
De uitgang van elke losse flipflop kan ook gebruikt worden; dit is nodig bij serieel-naar-parallel omzetting. Met extra logica en
signalen kunnen ook alle flipflops in één keer geladen worden, dit wordt gebruikt bij parallel-naar-serieel-omzetting.
Door extra logica toe te voegen is het ook mogelijk een schuifregister links of rechts te laten schuiven.
Een tijdsvolgordediagram in tabelvorm van een register van 6 bits: (registerinhoud na een klokpuls, beginwaarde 000000):
Ingang
Registerinhoud
Uitgang
0
000000
0
1
100000
0
1
110000
0
0
011000
0
1
101100
0
0
010110
0
1
101011
1
0
010101
1
0
001010
0
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sequential circuits
Combinational logic is useful for interesting operations like decoding, encoding, addition and subtraction. However, sequence
of operations are cumbersome to handle using combinational logic methods.
Combinatorial logic interconnected with storage elements gives rise to sequential circuits.
In combinational circuit, the output is only a function of all inputs and given any combination of inputs, it is always possible to
predict the output. In sequential circuit, the output is not only a function inputs but history of the input changes.
storage elements
Storage can be constructed logic with delay, such as a buffer by connecting the output to the input. The signal must not undergo
inversion in the loop or the system will be unstable or astable.
An important consequence of this type of feedback, called positive feedback, is that the behaviour of the system is highly dependent
on propagation delay of of the gates and timing of the input changes.
synchronous circuits
In asynchronous sequential circuits, input changes at any time may result in the any of of the outputs or internally stored information
(called state) to change. Such circuits are difficult to design because of dependence on propagation delays and their interaction
with timing of input changes.
A synchronous sequential makes use of clock signals so that the storage elements (and outputs) only change at discrete instants of
time in relation to the clock signal. Clocked synchronous circuits provide some degree of independence on timing variations related
to gate propagation delays.
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latch
A storage element maintains binary state indefinitely (as long as power is applied), until directed by an input signal to switch
to its other state.
The simplest latch, also referred to as the SR latch has two inputs and two outputs and can be constructed from two NOR
gates as shown.
The behaviour of the above latch in can be illustrated using the following timing diagram (unlike combinational circuits,
sequential circuits are a function of time) as shown below:
Note that when S and R simultaneously change from their asserted state to their deasserted states, the flip flop enters an
unstable state when its outputs oscillate between two binary states indefinitely.
An alternate form of the SR latch, in this case the set and reset signals active low, can be constructed using NAND gates as
follows:
One way to prevent the system from becoming unstable is by means of gating the set and reset inputs using a control input.
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Another way of eliminating the undesirable unstable state is by means of making sure that both set and reset signals are
never active at the same time giving rise to a what is called a D latch.
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flip-flops
In the case of a latch with control input, the when the control is enabled, the latch is in transparent mode, that is its output
changes its state according to the set and reset states. During this transparent mode, it is still possible for the outputs to
become unstable if both set and reset inputs change from asserted to deasserted states simultaneously.
We avoid this problem using master-slave flip-flop arrangement as illustrated below:
Note that it is impossible (well, almost) for both the set and reset inputs to be asserted for the slave latch on the right when
its control is enabled because the control of the master latch on the left is disabled at this time.
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J-K flip-flop
A modified version of the SR flip-flop which eliminates the unstable oscillation and indeterminate behaviour is the JK flip-flop.
edge-triggered flip-flops
The control signal in master-slave arrangement enables the master latch to be in transparent mode while it is high. Thus the
flip-flop is sensitive to inputs to the master for all the time its control signal is enabled.
In the case of edge triggered flip-flips, the control pulse is ignored while it is at a constant state and changes occur only
during a transition of the clock signal.
The above is an example of a positive edge triggered D-type flip-flop.
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flip-flop symbols
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characteristic tables
The characteristic able defines the logical properties of the flip-flop in the form of a table. The characteristic table for
sequential circuits is somewhat like the truth table for combinational logic circuits.
asynchronous inputs
Flip-flops often provide special inputs for setting or resetting them asynchronously, that is independently of the clock input.
The direct set and direct reset signals are called preset and clear, respectively.
Slide 192
Een condensator verzet zich tegen spanningsveranderingen en de spanning maakt nooit sprongen.
Capacitor Charge and Discharge
What happens when a capacitor is charging? How does charging really work? How does it discharge? Let's take a close look
at the basics. To help concentrate on the capacitor we assume the load is purely resistive, and ignore any effects of an
attached inductor.
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Key Principle: The guiding rule of nature is that current is the same everywhere in a series circuit. Charges will
move around, but are neither created nor destroyed. For charges to move, they must move identically everywhere
in a series circuit.
Discharge
Example: Suppose your capacitor is charged to 9 volts, and at time t =
0 the switch is connected to a one ohm resistor. The discharge time is
regulated by the resistance.
The initial current (t = 0) is I = V/R = (9 volts)/(1 ohm) = 9 amps.
For a moment, let's assume the rate of discharge is constant. That is, it
will follow a linear discharge curve over time. At this rate it would
discharge in time:
t = C * V / I = (0.022)*(9 volts)/(9 amps) = 0.022 sec = 22 milliseconds.
But! The rate is not actually linear. Our assumption was wrong, because
the current drops as the voltage drains away. This means it discharges
at a progressively slower rate over time. When the capacitor voltage
reaches 6 volts, there will only be 6 amps. When it's 3 volts, the current
is 3 amps. When it's down to 1 mV there's only 1 mA! An ideal
capacitor will never completely discharge! It will gradually approach zero volts but never quite reach it.
Exponential Decay
Exactly how does a capacitor discharge? From above, we see that capacitors do not discharge at a linear rate through
resistors.
When you do the math for a capacitor discharge, you get
an exponential decay curve: V(t) = V0 e-t / RC
This curve starts at the initial capacitor voltage (V0), and
diminishes quickly at first. As time goes on, the slope
becomes less and less while the voltage approaches (but
does not reach!) zero. However, for all practical purposes
the capacitor might as well be empty by the time 99% of
the initial charge has escaped.
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Shown at left is a comparison between a linear and exponential decay for this circuit. The exponential curve is a screen shot
taken from the RLC Simulator applet.
This graph shows that an exponential decay curve at 22 msec is only 64% discharged. Not only is it non-zero, but it isn't even
2/3 discharged yet! For this circuit at 40 msec, the exponential decay curve still has 16% of the original charge remaining.
Does a charged capacitor complete a circuit, or does it slowly discharge? In the figure at right, a switch connects a capacitor to
(a) a battery, then (b) unconnected, and finally (c) a low resistance. Let's study what happens in each position.
(A) Charge
With the switch at A, the capacitor is charging. Current
flows from the battery through the capacitor. The
electrons move to one plate, but they do not jump the
insulating gap inside the capacitor. They collect on the
surface of the plate.
Meanwhile, electrons are removed from the other plate
from the abundance that is always there in metals. That
gives the plate a net positive charge. And removing the charge completes the path around which current flows.
The current is always the same on both terminals of a capacitor. You can't move charge into one terminal without removing it
from the other.
As the current flows from the battery to the capacitor, it travels through the LED. This emits light during the charging cycle, and
then dims and finally turns dark when the capacitor is fully charged.
(B) Disconnected
With the switch at B, the capacitor is disconnected. What
happens? There is no current on one terminal of the
capacitor. There there must be no current on the other
terminal.
With no current flowing, the capacitor will keep its 9-volt
charge nearly forever. It is stored in the electric field
between the two places. It cannot move due to the
insulator -- the charges cannot jump the gap.
In practice, no insulator is perfect and the charge will eventually leak away. But this may take months in a high-quality capacitor.
Additionally, a significant charge can remain forever, stored in the chemical reaction that ionizes the plate surfaces of an
electrolytic capacitor. Be wary of old capacitors because they can bite!
(C) Discharge
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With the switch at C, the capacitor is connected to the 1ohm resistor. What happens? The charges stored in the
capacitor's electric field now have an escape route. They
can finally flow from one plate to the other, by travelling
through the resistor.
The rate of charge travel (current) depends on the circuit
resistance, and alos on how hard it is pushed by the
strength of the internal electric field (voltage).
Q: Does the capacitor need to discharge back to the battery, or to itself?
A: Neither. It can only discharge by being connected to something with a lower voltage, such as a resistor or coil. When you
move the switch to A then current will flow from the battery to the capacitor until their voltages are equal again.
Q: Where does it go? Can we run the current back into the capacitor, essentially recharging itself, or must it go back into the
battery?
A: The current (and capacitor's voltage) is gone. It was transformed into a small amount of heat in the resistor.
Q: How does the battery handle the power spike when the capacitor is connected?
A: Easily. When a battery (or capacitor) is connected to something with a lower voltage, current will flow. Batteries generate
current from an internal chemical reaction. Eventually all the chemicals finish combining with each other, and you need to
recharge (or recycle) the battery.
Current Myth
Electrons doesn't flow as fast or far as you might expect! Metal conductors contain a vast ocean of electrons, and only a small
number drift a short distance to provide all the current you need. This is a common misconception that is glossed over in
practically all text books (and my web pages too!). See "What Is Electricity?" by Bill Beatty to debunk some common
misconceptions!
Slide 245
CAS/RAS = Row Address Strobe/Column Address Strobe
Slide 246
Memory Read/Write timing cycles
The most important timing parameter to be considered in choosing a memory device is the access time. The maximum time
delay from an address input to a data output is longer than the delay between a chip enable and a data output, and
consequently the former timing figure is normally considered to be the access time. The access time for commonly used RAMs
varies from 50 to 500 ns.
For a read operation, once the output data are valid, the address input cannot be changed immediately to start another read
operation. This is because the device needs a certain amount of time, called read recovery time, to complete its internal
operations before the next memory operation. The sum of the access time and read recovery time is the memory read cycle
time. This is the time needed between the start of a read operation and the start of the next memory cycle.
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The memory write cycle time can be similarly defined and may be different from the read cycle time. The Figure below illustrates
the timing of a memory read cycle. The address is applied at point A, which is the beginning of the read cycle, and must be
held stable during the entire cycle. In order to reduce the access time, the chip enable input should be applied before point B.
The data output becomes valid after point C and remains valid as long as the address and chip enable inputs hold.
The R/W control input is not shown in the timing diagram for the read cycle, but should remain high throughout the entire cycle.
A typical write cycle is shown in Figure above. In addition to the address and chip enable inputs, an active low write pulse on
the R/W line and the data to be stored must be applied during the write cvcle. The timing of data input is less restrictive and can
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be satisfied simply by holding the data input stable during the entire cycle. However, the application of the write pulse has two
critical timing parameters: the address setup time and the write pulse width. The address setup time is the time required for the
address to stabilize and is the time that must elapse before the write pulse can be applied.
In the Figure above, the address setup time is the time interval between points A and B. The write pulse width defines the
amount of time that the write input must remain active low. The write cycle time is the time interval between points A and D and
is the sum of address setup time, write pulse width, and write recovery time.
It is important to note that the access time and cycle time discussed in this section are the minimum timing requirements for the
memory devices themselves. The access time and cycle time for the memory system as a whole are considerably longer
because of the delays resulting from the I/O control logic, system bus logic, and memory interface logic.
Slide 262
Fs>2 f0 <=> Fs/2>f0 => laagdoorlaatfilter voor alles >f0 voor dus alles >Fs/2 weg te filteren. (Signaal max freq is f0)
Martijn Saelens 2010