Download EPC9003 QSG.indd - Efficient Power Conversion

Figure 4: Waveforms for VIN = 170 V to 5 V/5 A (100kHz) Buck converter
CH1: VPWM Input voltage – CH4: (VOUT) Switch node voltage
NOTE. The EPC9003 development board does not have any current or thermal protection on board.
Figure 3: Proper Measurement of Switch Node – OUT
Minimize loop
EFFICIENT POWER CONVERSION
EPC
The EPC9003 development board showcases the EPC2010 eGaN FET. Although the electrical performance surpasses that for traditional Silicon
devices, their relatively smaller size does magnify the thermal management requirements. The EPC9003 is intended for bench evaluation with low
ambient temperature and convection cooling. The addition of heat-sinking and forced air cooling can significantly increase the current rating of
these devices, but care must be taken to not exceed the absolute maximum die temperature of 125°C.
Place probe in large via at OUT
Ground probe
against TP3
THERMAL CONSIDERATIONS
NOTE. When measuring the high frequency content switch node (OUT), care must be taken to avoid long ground leads. Measure the switch node (OUT) by placing the
oscilloscope probe tip through the large via on the switch node (designed for this purpose) and grounding the probe directly across the GND terminals provided. See
Figure 3 for proper scope probe technique.
EFFICIENT POWER CONVERSION
–
(For Efficiency
Measurement)
VDD
+
IIN
OUT
VIN
Gate Drive
Supply
Switch Node
Half-Bridge with Bypass
VIN Supply
+
<170 V
A
+
Gate Drive Supply
(Note Polarity)
VDD Supply
–
7 V – 12 V
EPC9003 – 200V DEVELOPMENT BOARD
Peter Cheng
FAE Support, Asia
Mobile: +886.938.009.706
[email protected]
Gate Drive
Regulator
–
VIN V
Enable
Level Shift,
Dead-time Adjust
and Gate Drive
Stephen Tsang
Sales, Asia
Mobile: +852.9408.8351
[email protected]
200 V Half-Bridge with Gate Drive, Using EPC2010
PWM
Input
External Circuit
Bhasy Nair
Global FAE Support
Office: +1.972.805.8585
Mobile: +1.469.879.2424
[email protected]
Quick Start Procedure
PWM Input
Figure 1: Block Diagram of EPC9003 Development Board
EPC
Renee Yawger
WW Marketing
Office: +1.908.475.5702
Mobile: +1.908.619.9678
[email protected]
Development board EPC9003 is easy to set up to evaluate the performance of the EPC2010 eGaN FET. Refer to Figure 2 for proper connect
and measurement setup and follow the procedure below:
Figure 2: Proper Connection and Measurement Setup
www.epc-co.com
Development Board EPC9003
Quick Start Guide
1. With power off, connect the input power supply bus to +VIN (J5, J6) and ground / return to –VIN (J7, J8).
2. With power off, connect the switch node of the half bridge OUT (J3, J4) to your circuit as required.
3. With power off, connect the gate drive input to +VDD (J1, Pin-1) and ground return to –VDD (J1, Pin-2).
4. With power off, connect the input PWM control signal to PWM (J2, Pin-1) and ground return to any of the remaining J2 pins.
5. Turn on the gate drive supply – make sure the supply is between 7 V and 12 V range.
6. Turn on the bus voltage to the required value (do not exceed the absolute maximum voltage of 200 V on VOUT).
7. Turn on the controller / PWM input source and probe switching node to see switching operation.
8. Once operational, adjust the bus voltage and load PWM control within the operating range and observe the output switching behavior,
efficiency and other parameters.
9. For shutdown, please follow steps in reverse.
Do not use probe ground lead
EPC9003 – 200V DEVELOPMENT BOARD
Contact us:
DESCRIPTION
www.epc-co.com
The EPC9003 development board is a 200 V maximum device voltage, 5 A maximum output current, half bridge with onboard gate
drives, featuring the EPC2010 enhancement mode (eGaN®) field
effect transistor (FET). The purpose of this development board is
to simplify the evaluation process of the EPC2010 eGaN FET by including all the critical components on a single board that can be
easily connected into any existing converter.
The EPC9003 development board is 2” x 1.5” and contains not
only two EPC2010 eGaN FET in a half bridge configuration
with gate drivers, but also an on board gate drive supply and
bypass capacitors. The board contains all critical components
and layout for optimal switching performance. There are also
various probe points to facilitate simple waveform measurement and efficiency calculation. A complete block diagram of
the circuit is given in Figure 1.
For more information on the EPC2010s eGaN FET please refer to
the datasheet available from EPC at www.epc-co.com. The datasheet should be read in conjunction with this quick start guide.
Table 1: Performance Summary (TA = 25°C)
SYMBOL PARAMETER
EPC Products are distributed exclusively through Digi-Key.
www.digikey.com
Development Board / Demonstration Board Notification
The EPC9003 board is intended for product evaluation purposes only and is not intended for commercial use. As an evaluation tool, it is not
designed for compliance with the European Union directive on electromagnetic compatibility or any other such directives or regulations.
As board builds are at times subject to product availability, it is possible that boards may contain components or assembly materials that are
not RoHS compliant. Efficient Power Conversion Corporation (EPC) makes no guarantee that the purchased board is 100% RoHS compliant.
No Licenses are implied or granted under any patent right or other intellectual property whatsoever. EPC assumes no liability for applications
assistance, customer product design, software performance, or infringement of patents or any other intellectual property rights of any kind.
EPC reserves the right at any time, without notice, to change said circuitry and specifications.
CONDITIONS
MIN
UNITS
VDD
Gate Drive Input Supply Range
12
V
VIN
Bus Input Voltage Range
170
V
VOUT
Switch Node Output Voltage
200
V
IOUT
Switch Node Output Current
VPWM
PWM Logic Input Voltage Threshold
7
MAX
5*
A
Input ‘High’
3.5
6
V
Input ‘Low’
0
1.5
V
Minimum ‘High’ State Input Pulse Width
VPWM rise and fall time < 10ns
60
ns
Minimum ‘Low’ State Input Pulse Width
VPWM rise and fall time < 10ns
500#
ns
* Assumes inductive load, maximum current depends on die temperature – actual maximum current with be subject to switching frequency, bus voltage and thermals.
# Dependent on time needed to ‘refresh’ high side bootstrap supply voltage.
Figure 4: Waveforms for VIN = 170 V to 5 V/5 A (100kHz) Buck converter
CH1: VPWM Input voltage – CH4: (VOUT) Switch node voltage
NOTE. The EPC9003 development board does not have any current or thermal protection on board.
Figure 3: Proper Measurement of Switch Node – OUT
Minimize loop
EFFICIENT POWER CONVERSION
EPC
The EPC9003 development board showcases the EPC2010 eGaN FET. Although the electrical performance surpasses that for traditional Silicon
devices, their relatively smaller size does magnify the thermal management requirements. The EPC9003 is intended for bench evaluation with low
ambient temperature and convection cooling. The addition of heat-sinking and forced air cooling can significantly increase the current rating of
these devices, but care must be taken to not exceed the absolute maximum die temperature of 125°C.
Place probe in large via at OUT
Ground probe
against TP3
THERMAL CONSIDERATIONS
NOTE. When measuring the high frequency content switch node (OUT), care must be taken to avoid long ground leads. Measure the switch node (OUT) by placing the
oscilloscope probe tip through the large via on the switch node (designed for this purpose) and grounding the probe directly across the GND terminals provided. See
Figure 3 for proper scope probe technique.
EFFICIENT POWER CONVERSION
–
(For Efficiency
Measurement)
VDD
+
IIN
OUT
VIN
Gate Drive
Supply
Switch Node
Half-Bridge with Bypass
VIN Supply
+
<170 V
A
+
Gate Drive Supply
(Note Polarity)
VDD Supply
–
7 V – 12 V
EPC9003 – 200V DEVELOPMENT BOARD
Peter Cheng
FAE Support, Asia
Mobile: +886.938.009.706
[email protected]
Gate Drive
Regulator
–
VIN V
Enable
Level Shift,
Dead-time Adjust
and Gate Drive
Stephen Tsang
Sales, Asia
Mobile: +852.9408.8351
[email protected]
200 V Half-Bridge with Gate Drive, Using EPC2010
PWM
Input
External Circuit
Bhasy Nair
Global FAE Support
Office: +1.972.805.8585
Mobile: +1.469.879.2424
[email protected]
Quick Start Procedure
PWM Input
Figure 1: Block Diagram of EPC9003 Development Board
EPC
Renee Yawger
WW Marketing
Office: +1.908.475.5702
Mobile: +1.908.619.9678
[email protected]
Development board EPC9003 is easy to set up to evaluate the performance of the EPC2010 eGaN FET. Refer to Figure 2 for proper connect
and measurement setup and follow the procedure below:
Figure 2: Proper Connection and Measurement Setup
www.epc-co.com
Development Board EPC9003
Quick Start Guide
1. With power off, connect the input power supply bus to +VIN (J5, J6) and ground / return to –VIN (J7, J8).
2. With power off, connect the switch node of the half bridge OUT (J3, J4) to your circuit as required.
3. With power off, connect the gate drive input to +VDD (J1, Pin-1) and ground return to –VDD (J1, Pin-2).
4. With power off, connect the input PWM control signal to PWM (J2, Pin-1) and ground return to any of the remaining J2 pins.
5. Turn on the gate drive supply – make sure the supply is between 7 V and 12 V range.
6. Turn on the bus voltage to the required value (do not exceed the absolute maximum voltage of 200 V on VOUT).
7. Turn on the controller / PWM input source and probe switching node to see switching operation.
8. Once operational, adjust the bus voltage and load PWM control within the operating range and observe the output switching behavior,
efficiency and other parameters.
9. For shutdown, please follow steps in reverse.
Do not use probe ground lead
EPC9003 – 200V DEVELOPMENT BOARD
Contact us:
DESCRIPTION
www.epc-co.com
The EPC9003 development board is a 200 V maximum device voltage, 5 A maximum output current, half bridge with onboard gate
drives, featuring the EPC2010 enhancement mode (eGaN®) field
effect transistor (FET). The purpose of this development board is
to simplify the evaluation process of the EPC2010 eGaN FET by including all the critical components on a single board that can be
easily connected into any existing converter.
The EPC9003 development board is 2” x 1.5” and contains not
only two EPC2010 eGaN FET in a half bridge configuration
with gate drivers, but also an on board gate drive supply and
bypass capacitors. The board contains all critical components
and layout for optimal switching performance. There are also
various probe points to facilitate simple waveform measurement and efficiency calculation. A complete block diagram of
the circuit is given in Figure 1.
For more information on the EPC2010s eGaN FET please refer to
the datasheet available from EPC at www.epc-co.com. The datasheet should be read in conjunction with this quick start guide.
Table 1: Performance Summary (TA = 25°C)
SYMBOL PARAMETER
EPC Products are distributed exclusively through Digi-Key.
www.digikey.com
Development Board / Demonstration Board Notification
The EPC9003 board is intended for product evaluation purposes only and is not intended for commercial use. As an evaluation tool, it is not
designed for compliance with the European Union directive on electromagnetic compatibility or any other such directives or regulations.
As board builds are at times subject to product availability, it is possible that boards may contain components or assembly materials that are
not RoHS compliant. Efficient Power Conversion Corporation (EPC) makes no guarantee that the purchased board is 100% RoHS compliant.
No Licenses are implied or granted under any patent right or other intellectual property whatsoever. EPC assumes no liability for applications
assistance, customer product design, software performance, or infringement of patents or any other intellectual property rights of any kind.
EPC reserves the right at any time, without notice, to change said circuitry and specifications.
CONDITIONS
MIN
UNITS
VDD
Gate Drive Input Supply Range
12
V
VIN
Bus Input Voltage Range
170
V
VOUT
Switch Node Output Voltage
200
V
IOUT
Switch Node Output Current
VPWM
PWM Logic Input Voltage Threshold
7
MAX
5*
A
Input ‘High’
3.5
6
V
Input ‘Low’
0
1.5
V
Minimum ‘High’ State Input Pulse Width
VPWM rise and fall time < 10ns
60
ns
Minimum ‘Low’ State Input Pulse Width
VPWM rise and fall time < 10ns
500#
ns
* Assumes inductive load, maximum current depends on die temperature – actual maximum current with be subject to switching frequency, bus voltage and thermals.
# Dependent on time needed to ‘refresh’ high side bootstrap supply voltage.
NOTE. The EPC9003 development board does not have any current or thermal protection on board.
Figure 4: Waveforms for VIN = 170 V to 5 V/5 A (100kHz) Buck converter
CH1: VPWM Input voltage – CH4: (VOUT) Switch node voltage
The EPC9003 development board showcases the EPC2010 eGaN FET. Although the electrical performance surpasses that for traditional Silicon
devices, their relatively smaller size does magnify the thermal management requirements. The EPC9003 is intended for bench evaluation with low
ambient temperature and convection cooling. The addition of heat-sinking and forced air cooling can significantly increase the current rating of
these devices, but care must be taken to not exceed the absolute maximum die temperature of 125°C.
Figure 3: Proper Measurement of Switch Node – OUT
EFFICIENT POWER CONVERSION
EPC
Minimize loop
Place probe in large via at OUT
Ground probe
against TP3
THERMAL CONSIDERATIONS
NOTE. When measuring the high frequency content switch node (OUT), care must be taken to avoid long ground leads. Measure the switch node (OUT) by placing the
oscilloscope probe tip through the large via on the switch node (designed for this purpose) and grounding the probe directly across the GND terminals provided. See
Figure 3 for proper scope probe technique.
Do not use probe ground lead
EPC9003 – 200V DEVELOPMENT BOARD
Figure 2: Proper Connection and Measurement Setup
EFFICIENT POWER CONVERSION
Figure 1: Block Diagram of EPC9003 Development Board
EPC
PWM Input
–
(For Efficiency
Measurement)
External Circuit
–
VIN V
Switch Node
+
IIN
OUT
VIN Supply
+
<170 V
A
+
Gate Drive Supply
(Note Polarity)
–
EPC9003 – 200V DEVELOPMENT BOARD
DESCRIPTION
Development Board EPC9003
Quick Start Guide
Contact us:
www.epc-co.com
Bhasy Nair
Global FAE Support
Office: +1.972.805.8585
Mobile: +1.469.879.2424
[email protected]
Level Shift,
Dead-time Adjust
and Gate Drive
VIN
VDD Supply
Half-Bridge with Bypass
7 V – 12 V
Renee Yawger
WW Marketing
Office: +1.908.475.5702
Mobile: +1.908.619.9678
[email protected]
Enable
Gate Drive
Regulator
Gate Drive
Supply
Peter Cheng
FAE Support, Asia
Mobile: +886.938.009.706
[email protected]
PWM
Input
VDD
Stephen Tsang
Sales, Asia
Mobile: +852.9408.8351
[email protected]
With power off, connect the input power supply bus to +VIN (J5, J6) and ground / return to –VIN (J7, J8).
With power off, connect the switch node of the half bridge OUT (J3, J4) to your circuit as required.
With power off, connect the gate drive input to +VDD (J1, Pin-1) and ground return to –VDD (J1, Pin-2).
With power off, connect the input PWM control signal to PWM (J2, Pin-1) and ground return to any of the remaining J2 pins.
Turn on the gate drive supply – make sure the supply is between 7 V and 12 V range.
Turn on the bus voltage to the required value (do not exceed the absolute maximum voltage of 200 V on VOUT).
Turn on the controller / PWM input source and probe switching node to see switching operation.
Once operational, adjust the bus voltage and load PWM control within the operating range and observe the output switching behavior,
efficiency and other parameters.
9. For shutdown, please follow steps in reverse.
1.
2.
3.
4.
5.
6.
7.
8.
Development board EPC9003 is easy to set up to evaluate the performance of the EPC2010 eGaN FET. Refer to Figure 2 for proper connect
and measurement setup and follow the procedure below:
Quick Start Procedure
www.epc-co.com
The EPC9003 development board is a 200 V maximum device voltage, 5 A maximum output current, half bridge with onboard gate
drives, featuring the EPC2010 enhancement mode (eGaN®) field
effect transistor (FET). The purpose of this development board is
to simplify the evaluation process of the EPC2010 eGaN FET by including all the critical components on a single board that can be
easily connected into any existing converter.
200 V Half-Bridge with Gate Drive, Using EPC2010
The EPC9003 development board is 2” x 1.5” and contains not
only two EPC2010 eGaN FET in a half bridge configuration
with gate drivers, but also an on board gate drive supply and
bypass capacitors. The board contains all critical components
and layout for optimal switching performance. There are also
various probe points to facilitate simple waveform measurement and efficiency calculation. A complete block diagram of
the circuit is given in Figure 1.
For more information on the EPC2010s eGaN FET please refer to
the datasheet available from EPC at www.epc-co.com. The datasheet should be read in conjunction with this quick start guide.
Table 1: Performance Summary (TA = 25°C)
SYMBOL PARAMETER
VDD
V
EPC Products are distributed exclusively through Digi-Key.
www.digikey.com
Development Board / Demonstration Board Notification
The EPC9003 board is intended for product evaluation purposes only and is not intended for commercial use. As an evaluation tool, it is not
designed for compliance with the European Union directive on electromagnetic compatibility or any other such directives or regulations.
As board builds are at times subject to product availability, it is possible that boards may contain components or assembly materials that are
not RoHS compliant. Efficient Power Conversion Corporation (EPC) makes no guarantee that the purchased board is 100% RoHS compliant.
No Licenses are implied or granted under any patent right or other intellectual property whatsoever. EPC assumes no liability for applications
assistance, customer product design, software performance, or infringement of patents or any other intellectual property rights of any kind.
IN
CONDITIONS
Gate Drive Input Supply Range
MIN
7
Bus Input Voltage Range
PWM Logic Input Voltage Threshold
VPWM
Switch Node Output Current
IOUT
Switch Node Output Voltage
VOUT
MAX
12
170
200
5*
0
Input ‘Low’
3.5
Input ‘High’
VPWM rise and fall time < 10ns
Minimum ‘Low’ State Input Pulse Width
VPWM rise and fall time < 10ns
Minimum ‘High’ State Input Pulse Width
6
1.5
60
UNITS
V
V
V
A
V
V
ns
ns
500#
* Assumes inductive load, maximum current depends on die temperature – actual maximum current with be subject to switching frequency, bus voltage and thermals.
# Dependent on time needed to ‘refresh’ high side bootstrap supply voltage.
EPC reserves the right at any time, without notice, to change said circuitry and specifications.
NOTE. The EPC9003 development board does not have any current or thermal protection on board.
Figure 4: Waveforms for VIN = 170 V to 5 V/5 A (100kHz) Buck converter
CH1: VPWM Input voltage – CH4: (VOUT) Switch node voltage
The EPC9003 development board showcases the EPC2010 eGaN FET. Although the electrical performance surpasses that for traditional Silicon
devices, their relatively smaller size does magnify the thermal management requirements. The EPC9003 is intended for bench evaluation with low
ambient temperature and convection cooling. The addition of heat-sinking and forced air cooling can significantly increase the current rating of
these devices, but care must be taken to not exceed the absolute maximum die temperature of 125°C.
Figure 3: Proper Measurement of Switch Node – OUT
EFFICIENT POWER CONVERSION
EPC
Minimize loop
Place probe in large via at OUT
Ground probe
against TP3
THERMAL CONSIDERATIONS
NOTE. When measuring the high frequency content switch node (OUT), care must be taken to avoid long ground leads. Measure the switch node (OUT) by placing the
oscilloscope probe tip through the large via on the switch node (designed for this purpose) and grounding the probe directly across the GND terminals provided. See
Figure 3 for proper scope probe technique.
Do not use probe ground lead
EPC9003 – 200V DEVELOPMENT BOARD
Figure 2: Proper Connection and Measurement Setup
EFFICIENT POWER CONVERSION
Figure 1: Block Diagram of EPC9003 Development Board
EPC
PWM Input
–
(For Efficiency
Measurement)
External Circuit
–
VIN V
Switch Node
+
IIN
OUT
VIN Supply
+
<170 V
A
+
Gate Drive Supply
(Note Polarity)
–
EPC9003 – 200V DEVELOPMENT BOARD
DESCRIPTION
Development Board EPC9003
Quick Start Guide
Contact us:
www.epc-co.com
Bhasy Nair
Global FAE Support
Office: +1.972.805.8585
Mobile: +1.469.879.2424
[email protected]
Level Shift,
Dead-time Adjust
and Gate Drive
VIN
VDD Supply
Half-Bridge with Bypass
7 V – 12 V
Renee Yawger
WW Marketing
Office: +1.908.475.5702
Mobile: +1.908.619.9678
[email protected]
Enable
Gate Drive
Regulator
Gate Drive
Supply
Peter Cheng
FAE Support, Asia
Mobile: +886.938.009.706
[email protected]
PWM
Input
VDD
Stephen Tsang
Sales, Asia
Mobile: +852.9408.8351
[email protected]
With power off, connect the input power supply bus to +VIN (J5, J6) and ground / return to –VIN (J7, J8).
With power off, connect the switch node of the half bridge OUT (J3, J4) to your circuit as required.
With power off, connect the gate drive input to +VDD (J1, Pin-1) and ground return to –VDD (J1, Pin-2).
With power off, connect the input PWM control signal to PWM (J2, Pin-1) and ground return to any of the remaining J2 pins.
Turn on the gate drive supply – make sure the supply is between 7 V and 12 V range.
Turn on the bus voltage to the required value (do not exceed the absolute maximum voltage of 200 V on VOUT).
Turn on the controller / PWM input source and probe switching node to see switching operation.
Once operational, adjust the bus voltage and load PWM control within the operating range and observe the output switching behavior,
efficiency and other parameters.
9. For shutdown, please follow steps in reverse.
1.
2.
3.
4.
5.
6.
7.
8.
Development board EPC9003 is easy to set up to evaluate the performance of the EPC2010 eGaN FET. Refer to Figure 2 for proper connect
and measurement setup and follow the procedure below:
Quick Start Procedure
www.epc-co.com
The EPC9003 development board is a 200 V maximum device voltage, 5 A maximum output current, half bridge with onboard gate
drives, featuring the EPC2010 enhancement mode (eGaN®) field
effect transistor (FET). The purpose of this development board is
to simplify the evaluation process of the EPC2010 eGaN FET by including all the critical components on a single board that can be
easily connected into any existing converter.
200 V Half-Bridge with Gate Drive, Using EPC2010
The EPC9003 development board is 2” x 1.5” and contains not
only two EPC2010 eGaN FET in a half bridge configuration
with gate drivers, but also an on board gate drive supply and
bypass capacitors. The board contains all critical components
and layout for optimal switching performance. There are also
various probe points to facilitate simple waveform measurement and efficiency calculation. A complete block diagram of
the circuit is given in Figure 1.
For more information on the EPC2010s eGaN FET please refer to
the datasheet available from EPC at www.epc-co.com. The datasheet should be read in conjunction with this quick start guide.
Table 1: Performance Summary (TA = 25°C)
SYMBOL PARAMETER
VDD
V
EPC Products are distributed exclusively through Digi-Key.
www.digikey.com
Development Board / Demonstration Board Notification
The EPC9003 board is intended for product evaluation purposes only and is not intended for commercial use. As an evaluation tool, it is not
designed for compliance with the European Union directive on electromagnetic compatibility or any other such directives or regulations.
As board builds are at times subject to product availability, it is possible that boards may contain components or assembly materials that are
not RoHS compliant. Efficient Power Conversion Corporation (EPC) makes no guarantee that the purchased board is 100% RoHS compliant.
No Licenses are implied or granted under any patent right or other intellectual property whatsoever. EPC assumes no liability for applications
assistance, customer product design, software performance, or infringement of patents or any other intellectual property rights of any kind.
IN
CONDITIONS
Gate Drive Input Supply Range
MIN
7
Bus Input Voltage Range
PWM Logic Input Voltage Threshold
VPWM
Switch Node Output Current
IOUT
Switch Node Output Voltage
VOUT
MAX
12
170
200
5*
0
Input ‘Low’
3.5
Input ‘High’
VPWM rise and fall time < 10ns
Minimum ‘Low’ State Input Pulse Width
VPWM rise and fall time < 10ns
Minimum ‘High’ State Input Pulse Width
6
1.5
60
UNITS
V
V
V
A
V
V
ns
ns
500#
* Assumes inductive load, maximum current depends on die temperature – actual maximum current with be subject to switching frequency, bus voltage and thermals.
# Dependent on time needed to ‘refresh’ high side bootstrap supply voltage.
EPC reserves the right at any time, without notice, to change said circuitry and specifications.
Table 2 : Bill of Material
Item
Qty
Reference
Part Description
Manufacturer / Part #
1
5
C1, C2, C3, C10, C11
Capacitor, 1uF, 10%, 25V, X5R
Murata, GRM188R61E105KA12D
2
2
C6, C7
Capacitor, 100pF, 5%, 50V, NP0
TDK, C1608C0G1H101J
3
4
C8, C9, C12, C13
Capacitor, 0.22uF, 10%, 16V, X7R
TDK, C1005X7R1C224K
4
3
C16, C17, C18
Capacitor, 0.1uF, 10%, 250V, X7T
C2012X7T2E104K125AA
5
2
D1, D2
Schottky Diode, 30V
Diodes Inc., SDM03U40-7
6
1
D3
Diode, 200V
Diodes Inc.,BAV21WS-7-F
7
2
D4, D5
Diode, 40V
Diodes Inc.,BAS40LP-7
8
1
J1
Connector
2pins of Tyco, 4-103185-0
9
1
J2
Connector
4pins of Tyco, 4-103185-0
10
1
J3, J4, J5, J6, J7, J8
Connector
FCI, 68602-224HLF
11
2
Q1, Q2
eGaNFET
EPC, EPC2010
12
1
R1
Resistor, 10.0K, 5%, 1/8W
Stackpole, RMCF0603FT10K0
13
2
R11, R12
Resistor, 0 Ohm, 1/16W
Stackpole, RMCF0402ZT0R00
14
4
R2, R3, R6, R15
Resistor, 0 Ohm, 1/8W
Stackpole, RMCF0603FT00R0
15
1
R4
Resistor, 100Ohm, 1%, 1/8W
Stackpole, RMCF0603FT100R
16
1
R5
Resistor, 470 Ohm, 1%, 1/8W
Stackpole, RMCF0603FT470R
17
2
TP1, TP2
Test Point
Keystone Elect, 5015
18
1
TP3
Connector
1/40th of Tyco, 4-103185-0
19
1
U1
I.C., Logic
Fairchild, NC7SZ00L6X
20
1
U2
I.C., Opto-coupler
Silicon Labs, Si8610BC
21
1
U4
I.C., Logic
Fairchild, NC7SZ08L6X
22
2
U6, U7
I.C., Gate driver
Texas Instruments, UCC27611
23
0
P1, P2
Optional potentiometer
24
0
R13
Optional resistor
25
0
U5
Optional I.C.
1
2
4
3
5
6
A
A
7 - 12 Vdc
J9
1
2
6
2
B
5
5
Y
4
3
GND
NC7SZ00L6X
CON2
C11
1uF, 25V
1uF, 25V
C6
100p
C8
2
0.22uF,
25V
3
U4
A
GND
P2
Optional
Y
1
2
3
4
J6
CON4
B
R11zero
EPC2010
J3
CON4
C16
C17
C18
0.1uF, 250V
J4
CON4
R3 Zero
2
U5
U7
1 VDD
VDD
C9
0.22uF, 25V
2
C13
0.22uF, 25V
LDO
VREF
5
4
3
C3
1uF, 25V
UCC27611
Optional
6
VSS
7
TP3
1
D5BAS40LP
Q2
R12zero
EPC2010
CON1
J7
CON4
C
GND
4
3
2
1
C7
100p
1
Q1
100
470
R15
Zero
D4BAS40LP
SW OUT
SDM03U40
R5
Optional
7
170V Max
VCC
D2
R14
5
4
SDM03U40
R4
NC7SZ08L6X
PWM2
6
UCC27611
P1
2
Optional
D1
VDD
LDO
VREF
VSS
SS8610BC
R2
Zero
B
C
1 VDD
C1
C2
1uF, 25V
C12
0.22uF, 25V
U6
U2
VCC
J5
CON4
4
3
2
1
VDD
TP2
Keystone 5015
1
2
3
4
R1
10k
U1
A
zero
C10
1uF, 25V
1
2
3
4
CON2
1
BAV21
R6
4
3
2
1
B
PWM1
1
2
CON2
J2
1
2
D3
VDD
J1
TP1
Keystone 5015
J8
CON4
D
D
200V Half-Bridge with Gate Drive, using EPC2010
Rev 3.0
1
2
3
4
5
6
Table 2 : Bill of Material
Item
Qty
Reference
Part Description
Manufacturer / Part #
1
5
C1, C2, C3, C10, C11
Capacitor, 1uF, 10%, 25V, X5R
Murata, GRM188R61E105KA12D
2
2
C6, C7
Capacitor, 100pF, 5%, 50V, NP0
TDK, C1608C0G1H101J
3
4
C8, C9, C12, C13
Capacitor, 0.22uF, 10%, 16V, X7R
TDK, C1005X7R1C224K
4
3
C16, C17, C18
Capacitor, 0.1uF, 10%, 250V, X7T
C2012X7T2E104K125AA
5
2
D1, D2
Schottky Diode, 30V
Diodes Inc., SDM03U40-7
6
1
D3
Diode, 200V
Diodes Inc.,BAV21WS-7-F
7
2
D4, D5
Diode, 40V
Diodes Inc.,BAS40LP-7
8
1
J1
Connector
2pins of Tyco, 4-103185-0
9
1
J2
Connector
4pins of Tyco, 4-103185-0
10
1
J3, J4, J5, J6, J7, J8
Connector
FCI, 68602-224HLF
11
2
Q1, Q2
eGaNFET
EPC, EPC2010
12
1
R1
Resistor, 10.0K, 5%, 1/8W
Stackpole, RMCF0603FT10K0
13
2
R11, R12
Resistor, 0 Ohm, 1/16W
Stackpole, RMCF0402ZT0R00
14
4
R2, R3, R6, R15
Resistor, 0 Ohm, 1/8W
Stackpole, RMCF0603FT00R0
15
1
R4
Resistor, 100Ohm, 1%, 1/8W
Stackpole, RMCF0603FT100R
16
1
R5
Resistor, 470 Ohm, 1%, 1/8W
Stackpole, RMCF0603FT470R
17
2
TP1, TP2
Test Point
Keystone Elect, 5015
18
1
TP3
Connector
1/40th of Tyco, 4-103185-0
19
1
U1
I.C., Logic
Fairchild, NC7SZ00L6X
20
1
U2
I.C., Opto-coupler
Silicon Labs, Si8610BC
21
1
U4
I.C., Logic
Fairchild, NC7SZ08L6X
22
2
U6, U7
I.C., Gate driver
Texas Instruments, UCC27611
23
0
P1, P2
Optional potentiometer
24
0
R13
Optional resistor
25
0
U5
Optional I.C.
1
2
4
3
5
6
A
A
7 - 12 Vdc
J9
1
2
6
2
B
5
5
Y
4
3
GND
NC7SZ00L6X
CON2
C11
1uF, 25V
1uF, 25V
C6
100p
C8
2
0.22uF,
16V
3
U4
A
GND
P2
Optional
Y
1
2
3
4
J6
CON4
B
R11zero
EPC2010
J3
CON4
C16
C17
C18
0.1uF, 250V
J4
CON4
R3 Zero
2
U5
U7
1 VDD
VDD
C9
0.22uF, 16V
2
C13
0.22uF, 16V
LDO
VREF
5
4
3
C3
1uF, 25V
UCC27611
Optional
6
VSS
7
TP3
1
D5 BAS40LP
Q2
R12zero
EPC2010
CON1
J7
CON4
C
GND
4
3
2
1
C7
100p
1
Q1
100
470
R15
Zero
D4 BAS40LP
SW OUT
SDM03U40
R5
Optional
7
170V Max
VCC
D2
R14
5
4
SDM03U40
R4
NC7SZ08L6X
PWM2
6
UCC27611
P1
2
Optional
D1
VDD
LDO
VREF
VSS
Si8610BC
R2
Zero
B
C
1 VDD
C1
C2
1uF, 25V
C12
0.22uF, 16V
U6
U2
VCC
J5
CON4
4
3
2
1
VDD
TP2
Keystone 5015
1
2
3
4
R1
10k
U1
A
zero
C10
1uF, 25V
1
2
3
4
CON2
1
BAV21
R6
4
3
2
1
B
PWM1
1
2
CON2
J2
1
2
D3
VDD
J1
TP1
Keystone 5015
J8
CON4
D
D
200V Half-Bridge with Gate Drive, using EPC2010
Rev 3.0
1
2
3
4
5
6
Figure 4: Waveforms for VIN = 170 V to 5 V/5 A (100kHz) Buck converter
CH1: VPWM Input voltage – CH4: (VOUT) Switch node voltage
NOTE. The EPC9003 development board does not have any current or thermal protection on board.
Figure 3: Proper Measurement of Switch Node – OUT
Minimize loop
EFFICIENT POWER CONVERSION
EPC
The EPC9003 development board showcases the EPC2010 eGaN FET. Although the electrical performance surpasses that for traditional Silicon
devices, their relatively smaller size does magnify the thermal management requirements. The EPC9003 is intended for bench evaluation with low
ambient temperature and convection cooling. The addition of heat-sinking and forced air cooling can significantly increase the current rating of
these devices, but care must be taken to not exceed the absolute maximum die temperature of 125°C.
Place probe in large via at OUT
Ground probe
against TP3
THERMAL CONSIDERATIONS
NOTE. When measuring the high frequency content switch node (OUT), care must be taken to avoid long ground leads. Measure the switch node (OUT) by placing the
oscilloscope probe tip through the large via on the switch node (designed for this purpose) and grounding the probe directly across the GND terminals provided. See
Figure 3 for proper scope probe technique.
EFFICIENT POWER CONVERSION
–
(For Efficiency
Measurement)
PWM
Input
VDD
Switch Node
+
IIN
OUT
VIN
Gate Drive
Supply
–
VIN V
Enable
Level Shift,
Dead-time Adjust
and Gate Drive
Gate Drive
Regulator
External Circuit
Half-Bridge with Bypass
VIN Supply
+
<170 V
A
+
Gate Drive Supply
(Note Polarity)
VDD Supply
–
7 V – 12 V
EPC9003 – 200V DEVELOPMENT BOARD
Visit our website:
www.epc-co.com
200 V Half-Bridge with Gate Drive, Using EPC2010
Quick Start Procedure
PWM Input
Figure 1: Block Diagram of EPC9003 Development Board
EPC
Please contact [email protected]
or your local sales representative
Development board EPC9003 is easy to set up to evaluate the performance of the EPC2010 eGaN FET. Refer to Figure 2 for proper connect
and measurement setup and follow the procedure below:
Figure 2: Proper Connection and Measurement Setup
For More Information:
1. With power off, connect the input power supply bus to +VIN (J5, J6) and ground / return to –VIN (J7, J8).
2. With power off, connect the switch node of the half bridge OUT (J3, J4) to your circuit as required.
3. With power off, connect the gate drive input to +VDD (J1, Pin-1) and ground return to –VDD (J1, Pin-2).
4. With power off, connect the input PWM control signal to PWM (J2, Pin-1) and ground return to any of the remaining J2 pins.
5. Turn on the gate drive supply – make sure the supply is between 7 V and 12 V range.
6. Turn on the bus voltage to the required value (do not exceed the absolute maximum voltage of 200 V on VOUT).
7. Turn on the controller / PWM input source and probe switching node to see switching operation.
8. Once operational, adjust the bus voltage and load PWM control within the operating range and observe the output switching behavior,
efficiency and other parameters.
9. For shutdown, please follow steps in reverse.
Do not use probe ground lead
EPC9003 – 200V DEVELOPMENT BOARD
Development Board EPC9003
Quick Start Guide
DESCRIPTION
www.epc-co.com
The EPC9003 development board is a 200 V maximum device voltage, 5 A maximum output current, half bridge with onboard gate
drives, featuring the EPC2010 enhancement mode (eGaN®) field
effect transistor (FET). The purpose of this development board is
to simplify the evaluation process of the EPC2010 eGaN FET by including all the critical components on a single board that can be
easily connected into any existing converter.
The EPC9003 development board is 2” x 1.5” and contains not
only two EPC2010 eGaN FET in a half bridge configuration
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EPC updates at
bit.ly/EPCupdates
or text “EPC” to 22828
with gate drivers, but also an on board gate drive supply and
bypass capacitors. The board contains all critical components
and layout for optimal switching performance. There are also
various probe points to facilitate simple waveform measurement and efficiency calculation. A complete block diagram of
the circuit is given in Figure 1.
For more information on the EPC2010s eGaN FET please refer to
the datasheet available from EPC at www.epc-co.com. The datasheet should be read in conjunction with this quick start guide.
Table 1: Performance Summary (TA = 25°C)
SYMBOL PARAMETER
EPC Products are distributed through Digi-Key.
www.digikey.com
Development Board / Demonstration Board Notification
The EPC9003 board is intended for product evaluation purposes only and is not intended for commercial use. As an evaluation tool, it is not
designed for compliance with the European Union directive on electromagnetic compatibility or any other such directives or regulations.
As board builds are at times subject to product availability, it is possible that boards may contain components or assembly materials that are
not RoHS compliant. Efficient Power Conversion Corporation (EPC) makes no guarantee that the purchased board is 100% RoHS compliant.
No Licenses are implied or granted under any patent right or other intellectual property whatsoever. EPC assumes no liability for applications
assistance, customer product design, software performance, or infringement of patents or any other intellectual property rights of any kind.
EPC reserves the right at any time, without notice, to change said circuitry and specifications.
CONDITIONS
MIN
UNITS
VDD
Gate Drive Input Supply Range
12
V
VIN
Bus Input Voltage Range
170
V
VOUT
Switch Node Output Voltage
200
V
IOUT
Switch Node Output Current
VPWM
PWM Logic Input Voltage Threshold
7
MAX
5*
A
Input ‘High’
3.5
6
V
Input ‘Low’
0
1.5
V
Minimum ‘High’ State Input Pulse Width
VPWM rise and fall time < 10ns
60
ns
Minimum ‘Low’ State Input Pulse Width
VPWM rise and fall time < 10ns
500#
ns
* Assumes inductive load, maximum current depends on die temperature – actual maximum current with be subject to switching frequency, bus voltage and thermals.
# Dependent on time needed to ‘refresh’ high side bootstrap supply voltage.