Download LM567 - tone decoder

Philips Semiconductors Linear Products
Product specification
Tone decoder/phase-locked loop
NE/SE567
DESCRIPTION
PIN CONFIGURATIONS
The NE/SE567 tone and frequency decoder is a highly stable
phase-locked loop with synchronous AM lock detection and power
output circuitry. Its primary function is to drive a load whenever a
sustained frequency within its detection band is present at the
self-biased input. The bandwidth center frequency and output delay
are independently determined by means of four external
components.
FE, D, N Packages
OUTPUT FILTER
CAPACITOR C3
LOW-PASS FILTER
CAPACITOR C2
1
8
OUTPUT
2
7
INPUT
3
6
SUPPLY VOLTAGE V+
4
5
GROUND
TIMING
ELEMENTS R1
AND C1
TIMING ELEMENT R1
TOP VIEW
FEATURES
F Package
• Wide frequency range (.01Hz to 500kHz)
• High stability of center frequency
• Independently controllable bandwidth (up to 14%)
• High out-band signal and noise rejection
• Logic-compatible output with 100mA current sinking capability
• Inherent immunity to false signals
• Frequency adjustment over a 20-to-1 range with an external
OUTPUT 1
14 GND
C3 2
13 NC
NC 3
12 NC
C2 4
11 R1C1
INPUT 5
resistor
• Military processing available
10 R1
NC 6
9
NC
VCC 7
8
NC
TOP VIEW
• Frequency monitoring and control
• Wireless intercom
• Precision oscillator
APPLICATIONS
• Touch-Tone decoding
• Carrier current remote controls
• Ultrasonic controls (remote TV, etc.)
• Communications paging
BLOCK DIAGRAM
4
R2
3.9k
PHASE
DETECTOR
3
INPUT
V1
R1
2
LOOP
LOW
PASS
FILTER
C2
5
CURRENT
CONTROLLED
OSCILLATOR
6
AMP
C1
R3
+
QUADRATURE
PHASE
DETECTOR
–
VREF
AMP
8
RL
+V
7
1
C3 OUTPUT
FILTER
Touch-Tone is a registered trademark of AT&T.
April 15, 1992
403
853-0124 06456
April 15, 1992
C1
6
R1
5
Q3
R5
4
Q8
404
Q5
Q9
Q7
Q6
–V
Q13
Q12
R7
R4
Q10
R6
A
D
Q17
R19
Q22
Q27
Q29
R18
B
B
Q26
R24
R23
B
R22
Q21
Q20
R21
Q28
R17
Q30
Q23
R14
R16
EF
R13
R20
–V
Q18
R11
Q25 Q24
Q16
Q14 Q16
R10
–V
R15
R12
Q19
R9
A
Vi
2
3
R28
Q31
R26
Q32
B
R36
R30
–V
C2
Q34 Q35
R29
Cc
R26
R2
10k
Q36 Q37
R27
Q33
Q61
C
R48
21k
R48
21k
R36
Q38
Q30
Q50
R37
Q62
R36
Q40
Q40
R33
R32
R34
R40
E
Q59
Vref
R39
5k
F
R48
Q43
Q47 Q46
R43
C
R3
4.7k
Q41
Q42
B
Q45 Q44
R44
R49
Q58
Q54
R42
Q56 Q57
Q60
Q55
Q63
R41
1
Q61
R45
B
Q62
–V
RL
C3
Tone decoder/phase-locked loop
7
Q2
Q1
–V
Philips Semiconductors Linear Products
Product specification
NE/SE567
EQUIVALENT SCHEMATIC
Philips Semiconductors Linear Products
Product specification
Tone decoder/phase-locked loop
NE/SE567
ORDERING INFORMATION
TEMPERATURE RANGE
ORDER CODE
DWG #
8-Pin Plastic SO
DESCRIPTION
0 to +70°C
NE567D
0174C
14-Pin Cerdip
0 to +70°C
NE567F
0581B
8-Pin Plastic DIP
0 to +70°C
NE567N
0404B
8-Pin Plastic SO
-55°C to +125°C
SE567D
0174C
8-Pin Cerdip
-55°C to +125°C
SE567FE
0581B
8-Pin Plastic DIP
-55°C to +125°C
SE567N
0404B
ABSOLUTE MAXIMUM RATINGS
SYMBOL
TA
PARAMETER
RATING
UNIT
NE567
0 to +70
°C
SE567
-55 to +125
°C
10
V
Operating temperature
VCC
Operating voltage
V+
Positive voltage at input
0.5 +VS
V
V-
Negative voltage at input
-10
VDC
VOUT
Output voltage (collector of output transistor)
15
VDC
TSTG
Storage temperature range
PD
Power dissipation
April 15, 1992
405
-65 to +150
°C
300
mW
Philips Semiconductors Linear Products
Product specification
Tone decoder/phase-locked loop
NE/SE567
DC ELECTRICAL CHARACTERISTICS
V +=5.0V; TA=25°C, unless otherwise specified.
SYMBOL
PARAMETER
TEST CONDITIONS
SE567
Min
Center
frequency1
fO
Highest center frequency
fO
Center frequency stability2
fO
Center frequency distribution
fO
Center frequency shift with supply
voltage
-55 to +125°C
Max
Min
1
100kHz 1.1R 1C 1
f O 100kHz 1
1.1R 1C 1
f O 100kHz 1
1.1R 1C 1
-10
Typ
UNIT
Max
500
500
kHz
35 ±140
35 ±140
ppm/°C
35 ±60
0 to +70°C
fO
Typ
NE567
35 ±60
0
+10
0.5
1
14
16
2
4
-10
ppm/°C
0
+10
%
0.7
2
%/V
14
18
% of fO
3
6
% of fO
Detection bandwidth
BW
Largest detection bandwidth
BW
Largest detection bandwidth skew
BW
Largest detection bandwidth—
12
10
VI=300mVRMS
±0.1
±0.1
%/°C
VI=300mVRMS
±2
±2
%/V
variation with temperature
BW
Largest detection bandwidth—
variation with supply voltage
Input
RIN
Input resistance
VI
Smallest detectable input voltage4
IL=100mA, fI=fO
15
Largest no-output input voltage4
IL=100mA, fI=fO
10
Greatest simultaneous out-band
20
25
20
25
15
15
10
20
25
kΩ
20
25
mVRMS
15
mVRMS
+6
+6
dB
-6
-6
dB
signal-to-in-band signal ratio
Minimum input signal to wide-band
noise ratio
Bn=140kHz
Output
Fastest on-off cycling rate
fO/20
fO/20
“1” output leakage current
V8=15V
0.01
25
0.01
25
µA
“0” output voltage
IL=30mA
0.2
0.4
0.2
0.4
V
IL=100mA
0.6
1.0
0.6
1.0
V
time3
tF
Output fall
tR
Output rise time3
RL=50Ω
30
30
ns
RL=50Ω
150
150
ns
General
VCC
Operating voltage range
4.75
Supply current quiescent
Supply current—activated
tPD
RL=20kΩ
Quiescent power dissipation
9.0
V
6
9.0
8
7
10
mA
11
13
12
15
30
NOTES:
1. Frequency determining resistor R1 should be between 2 and 20kΩ
2. Applicable over 4.75V to 5.75V. See graphs for more detailed information.
3. Pin 8 to Pin 1 feedback RL network selected to eliminate pulsing during turn-on and turn-off.
4. With R2=130kΩ from Pin 1 to V+. See Figure 1.
April 15, 1992
406
4.75
35
mA
mW
Philips Semiconductors Linear Products
Product specification
Tone decoder/phase-locked loop
NE/SE567
TYPICAL PERFORMANCE CHARACTERISTICS
LARGEST BANDWIDTH — % OF O
f
300
250
INPUT VOLTAGE — mVrms
Largest Detection bandwidth
vs Operating Frequency
(Hz * µ F)
Bandwidth vs Input
Signal Amplitude
200
150
100
50
0
0
2
4
6
8
10 12 14
BANDWIDTH — % OF fO
16
Detection bandwidth as a
Function of C2 and C3
15
106
10
105
5
104
0
103
C3
0.1
Typical Supply Current vs
Supply Voltage
1
10
100
CENTER FREQUENCY — kHz
C2
0
1000
2
Greatest Number of Cycles
Before Output
16
Typical Output Voltage vs
Temperature
1.0
1000
25
4
6
8
10 12 14
BANDWIDTH — % OF fO
NO LOAD
“ON” CURRENT
BANDWIDTH LIMITED BY
EXTERNAL RESISTOR
(MINIMUM C2)
300
CYCLES
CUPPLY CURRENT — mA
20
15
10
100
50
QUIESCENT
CURRENT
5
BANDWIDTH
LIMITED BY (C2)
30
0
5
6
7
8
9
10
0.8
IL = 100mA
0.7
0.6
0.5
0.4
0.3
IL = 30mA
0.2
0.1
10
4
OUTPUT VOLTAGE PIN 8 — V
0.9
500
0
1
5
10
50
100
–75
SUPPLY VOLTAGE — V
Typical Frequency Drift
With Temperature
(Mean and SD)
1.5
(2)
1.0
1.0
2.5
0.5
0.5
0
0
0
–2.5
–0.5
–0.5
–5.0
–1.0
–1.0
–7.5
–1.5
25
75
TEMPERATURE — °C
April 15, 1992
75
125
5.5
+V = 5.75V
0
25
Typical Frequency Drift
With Temperature
(Mean and SD)
1.5
+V = 4.75V
–25
0
TEMPERATURE — °C
Typical Frequency Drift
With Temperature
(Mean and SD)
–75
–25
BANDWIDTH — % OF fO
125
–1.5
–75
+V = 7.0V (1)
+V = 9.0V (2)
(1)
–10
–25
0
25
75
TEMPERATURE — °C
407
125
–75
–25
0
25
75
TEMPERATURE — °C
125
Philips Semiconductors Linear Products
Product specification
Tone decoder/phase-locked loop
NE/SE567
TYPICAL PERFORMANCE CHARACTERISTICS (Continued)
Center Frequency
Shift With Supply
Voltage Change vs
Operating Frequency
Typical Bandwidth Variation
Temperature
100
1.0
15.0
14
0.9
0
12
12.5
0.8
BANDWIDTH — % OF f O
TEMPERATURE COEFFICIENT— ppm/ ° C
Center Frequency Temperature
Coefficient
(Mean and SD)
0.7
t
–100
t
O
O
ń V *
0.6
%ń V
0.5
0.4
–200
0.3
∆t = 0°C to 70°C
0.2
–300
10
10.0
8
7.5
6
5.0
4
2.5
2
0.1
4.5
5.0
5.5
6.0
6.5
7.0
SUPPLY VOLTAGE — V
BANDWIDTH AT 25°C
0
0
1
2
3 4 5
10
20
40
100
–75
–25
CENTER FREQUENCY — kHz
DESIGN FORMULAS
fO [
BW [
VI v
Ǹ
75
125
Figure 1 shows a typical connection diagram for the 567. For most
applications, the following three-step procedure will be sufficient for
choosing the external components R1, C1, C2 and C3.
1. Select R1 and C1 for the desired center frequency. For best
temperature stability, R1 should be between 2K and 20K ohm,
and the combined temperature coefficient of the R1C1 product
should have sufficient stability over the projected temperature
range to meet the necessary requirements.
VI
in % of f O
fO C2
200mV RMS
Where
VI=Input voltage (VRMS)
C2=Low-pass filter capacitor (µF)
2. Select the low-pass capacitor, C2, by referring to the Bandwidth
versus Input Signal Amplitude graph. If the input amplitude
Variation is known, the appropriate value of fO ⋅ C2 necessary to
give the desired bandwidth may be found. Conversely, an area of
operation may be selected on this graph and the input level and
C2 may be adjusted accordingly. For example, constant
bandwidth operation requires that input amplitude be above
200mVRMS. The bandwidth, as noted on the graph, is then
controlled solely by the fO ⋅ C2 product (fO (Hz), C2(µF)).
PHASE-LOCKED LOOP TERMINOLOGY CENTER
FREQUENCY (fO)
The free-running frequency of the current controlled oscillator (CCO)
in the absence of an input signal.
Detection Bandwidth (BW)
The frequency range, centered about fO, within which an input signal
above the threshold voltage (typically 20mVRMS) will cause a logical
zero state on the output. The detection bandwidth corresponds to
the loop capture range.
Lock Range
The largest frequency range within which an input signal above the
threshold voltage will hold a logical zero state on the output.
Detection Band Skew
A measure of how well the detection band is centered about the
center frequency, fO. The skew is defined as (fMAX+fMIN-2fO)/2fO
where fmax and fmin are the frequencies corresponding to the
edges of the detection band. The skew can be reduced to zero if
necessary by means of an optional centering adjustment.
April 15, 1992
25
OPERATING INSTRUCTIONS
1
1.1R 1 C 1
1070
0
TEMPERATURE – °C
408
Philips Semiconductors Linear Products
Product specification
Tone decoder/phase-locked loop
NE/SE567
saturates; its collector voltage being less than 1.0 volt (typically
0.6V) at full output current (100mA). The voltage at Pin 2 is the
phase detector output which is a linear function of frequency over
the range of 0.95 to 1.05 fO with a slope of about 20mV per percent
of frequency deviation. The average voltage at Pin 1 is, during lock,
a function of the in-band input amplitude in accordance with the
transfer characteristic given. Pin 5 is the controlled oscillator square
wave output of magnitude (+V -2VBE)≅(+V-1.4V) having a DC
average of +V/2. A 1kΩ load may be driven from pin 5. Pin 6 is an
exponential triangle of 1VP-P with an average DC level of +V/2. Only
high impedance loads may be
TYPICAL RESPONSE
INPUT
OUTPUT
NOTE:
RL = 100Ω
Response to 100mVRMS Tone Burst
OUTPUT
OUTPUT
(PIN 8)
V+
7% 14% BW
0
VCE (SAT) < 1.0V
INPUT
NOTES:
S/N = –6dB
RL = 100Ω
Noise Bandwidth = 140Hz
3.9V
LOW PASS
FILTER
(PIN 2)
3.8V
3.7V
Response to Same Input Tone Burst
With Wideband Noise
3. The value of C3 is generally non-critical. C3 sets the band edge
of a low-pass filter which attenuates frequencies outside the
detection band to eliminate spurious outputs. If C3 is too small,
frequencies just outside the detection band will switch the output
stage on and off at the beat frequency, or the output may pulse
on and off during the turn-on transient. If C3 is too large, turn-on
and turn-off of the
0.9fO
PIN 1
VOLTAGE
(AVG) 4.0
fO
1.1fO
VREF
THRESHOLD VOLTAGE
3.5
3.0
+V
INPUT
4
3
f1 = fO
+V
2.5
0
100
IN-BAND
INPUT
VOLTAGE
RL
Figure 2. Typical Output Response
5
f
O
6
C1
8
567
R1
1
R 1C 1
R2
2
7
C2
LOW
PASS
FILTER
1
C3
OUTPUT
FILTER
Figure 1.
output stage will be delayed until the voltage on C3 passes the
threshold voltage. (Such delay may be desirable to avoid spurious
outputs due to transient frequencies.) A typical minimum value for
C3 is 2C2.
4. Optional resistor R2 sets the threshold for the largest “no output”
input voltage. A value of 130kΩ is used to assure the tested limit
of 10mVRMS min. This resistor can be referenced to ground for
increased sensitivity. The explanation can be found in the
“optional controls” section which follows.
AVAILABLE OUTPUTS (Figure 1)
The primary output is the uncommitted output transistor collector,
Pin 8. When an in-band input signal is present, this transistor
April 15, 1992
200mVrms
409
Philips Semiconductors Linear Products
Product specification
Tone decoder/phase-locked loop
NE/SE567
cause supply voltage fluctuations which could, for example, shift the
detection band of narrow-band systems sufficiently to cause
momentary loss of lock. The result is a low-frequency oscillation into
and out of lock. Such effects can be prevented by supplying heavy
load currents from a separate supply or increasing the supply filter
capacitor.
V+
R
567 1
567 1
C3
C3
R
SPEED OF OPERATION
DECREASE
SENSITIVITY
Minimum lock-up time is related to the natural frequency of the loop.
The lower it is, the longer becomes the turn-on transient. Thus,
maximum operating speed is obtained when C2 is at a minimum.
When the signal is first applied, the phase may be such as to initially
drive the controlled oscillator away from the incoming frequency
rather than toward it. Under this condition, which is of course
unpredictable, the lock-up transient is at its worst and the theoretical
minimum lock-up time is not achievable. We must simply wait for the
transient to die out.
INCREASE
SENSITIVITY
V+
RA
567 1
50k
C3
RB
2.5k
RC
1.0k
DECREASE
SENSITIVITY
INCREASE
SENSITIVITY
SILICON
DIODES FOR
TEMPERATURE
COMPENSATION
(OPTIONAL)
The following expressions give the values of C2 and C3 which allow
highest operating speeds for various band center frequencies. The
minimum rate at which digital information may be detected without
information loss due to the turn-on transient or output chatter is
about 10 cycles per bit, corresponding to an information transfer rate
of fO/10 baud.
Figure 3. Sensitivity Adjust
connected to pin 6 without affecting the CCO duty cycle or
temperature stability.
V+
RL
OPERATING PRECAUTIONS
A brief review of the following precautions will help the user achieve
the high level of performance of which the 567 is capable.
567
8
567
1
Rf
10k
Cf
C3
C3
Rf*
10k
Rf
10k
1
567
8
RA
200 TO
1k
*OPTIONAL - PERMITS
LOWER VALUE OF Cf
Figure 4. Chatter Prevention
V+
2. The 567 will lock onto signals near (2n+1) fO, and will give an
output for signals near (4n+1) fO where n=0, 1, 2, etc. Thus,
signals at 5fO and 9fO can cause an unwanted output. If such
signals are anticipated, they should be attenuated before
reaching the 567 input.
3. Maximum immunity from noise and out-band signals is afforded
in the low input level (below 200mVRMS) and reduced bandwidth
operating mode. However, decreased loop damping causes the
worst-case lock-up time to increase, as shown by the Greatest
Number of Cycles Before Output vs Bandwidth graph.
R
567 2
567 2
C2
LOWERS fO
RAISES fO
C2
R
V+
LOWERS fO
RA
4. Due to the high switching speeds (20ns) associated with 567
operation, care should be taken in lead routing. Lead lengths
should be kept to a minimum. The power supply should be
adequately bypassed close to the 567 with a 0.01µF or greater
capacitor; grounding paths should be carefully chosen to avoid
ground loops and unwanted voltage variations. Another factor
which must be considered is the effect of load energization on
the power supply. For example, an incandescent lamp typically
draws 10 times rated current at turn-on. This can be somewhat
greater when the output stage is made less sensitive, rejection of
third harmonics or in-band harmonics (of lower frequency
signals) is also improved.
April 15, 1992
8
V+
RA
200 TO 1k
RL
1
1. Operation in the high input level mode (above 200mV) will free
the user from bandwidth variations due to changes in the in-band
signal amplitude. The input
stage is now limiting, however, so that out-band signals or high
noise levels can cause an apparent bandwidth reduction as the
inband signal is suppressed. Also, the limiting action will create
in-band components from sub-harmonic signals, so the 567
becomes sensitive to signals at fO/3, fO/5, etc.
V+
V+
567 1
50k
C2
RAISES fO
RB
2.5k
RC
1.0k
RAISES fO
SILICON
DIODES FOR
TEMPERATURE
COMPENSATION
(OPTIONAL)
Figure 5. Skew Adjust
410
RL
Philips Semiconductors Linear Products
Product specification
Tone decoder/phase-locked loop
C2 +
130
m F
fO
C3 +
260
m F
fO
NE/SE567
SENSITIVITY ADJUSTMENT (Figure 3)
When operated as a very narrow-band detector (less than 8
percent), both C2 and C3 are made quite large in order to improve
noise and out-band signal rejection. This will inevitably slow the
response time. If, however, the output stage is biased closer to the
threshold level, the turn-on time can be
improved. This is accomplished by drawing additional current to
terminal 1. Under this condition, the 567 will also give an output for
lower-level signals (10mV or lower).
In cases where turn-off time can be sacrificed to achieve fast
turn-on, the optional sensitivity adjustment circuit can be used to
move the quiescent C3 voltage lower (closer to the threshold
voltage). However, sensitivity to beat frequencies, noise and
extraneous signals will be increased.
By adding current to terminal 1, the output stage is biased further
away from the threshold voltage. This is most useful when, to obtain
maximum operating speed, C2 and C3 are made very small.
Normally, frequencies just outside the detection band could cause
false outputs under this condition. By desensitizing the output stage,
the out-band beat notes do not feed through to the output stage.
Since the input level must
OPTIONAL CONTROLS (Figure 3)
The 567 has been designed so that, for most applications, no
external adjustments are required. Certain applications, however,
will be greatly facilitated if full advantage is taken of the added
control possibilities available through the use of additional external
components. In the diagrams given, typical
values are suggested where applicable. For best results the
resistors used, except where noted, should have the same
temperature coefficient. Ideally, silicon diodes would be
low-resistivity types, such as forward-biased transistor base-emitter
junctions. However, ordinary low-voltage diodes should be adequate
for most applications.
V+
V+
RL
567 8
1
RA
10k
250
0.5k 0.9k 1.4k 1.9k
2.5k 3.2k 4.0k
UNLATCH
200
INPUT VOLTAGE MV — RMS
Rf
20k
C3
CA
10k
150
V+
V+
20k
RL
100
567 8
100k
UNLATCH
1
50
R
0
Rf
20k
0
2
4
6
8
10
12
14
C3
16
DETECTION BAND — % OF fO
NOTE:
CA prevents latch-up when power supply is turned on.
V+
PIN 2
567
RA
50k
Figure 7. Output Latching
RB
R + R
C2
A
)
R BR
C
RB )
R
C
RC
OPTIONAL SILICON
DIODES FOR
TEMPERATURE
COMPENSATION
NOTE:
130
f
O
ǒ 10k R) RǓ
t
C2 t
ǒ
1300 10k )
R
f
O
R
Ǔ
Adjust control for symmetry of detection band edges
about fO.
Figure 6. BW Reduction
April 15, 1992
411
Philips Semiconductors Linear Products
Product specification
Tone decoder/phase-locked loop
NE/SE567
CHATTER PREVENTION (Figure 4)
ALTERNATE METHOD OF BANDWIDTH
REDUCTION (Figure 6)
Chatter occurs in the output stage when C3 is relatively small, so
that the lock transient and the AC components at the quadrature
phase detector (lock detector) output cause the output stage to
move through its threshold more than once. Many loads, for
example lamps and relays, will not respond to the chatter. However,
logic may recognize the chatter as a series of outputs. By feeding
the output stage output back to its input (Pin 1) the chatter can be
eliminated. Three schemes for doing this are given in Figure 4. All
operate by feeding the first output step (either on or off) back to the
input, pushing the input past the threshold until the transient
conditions are over. It is only necessary to assure that the feedback
time constant is not so large as to prevent operation at the highest
anticipated speed. Although chatter can always be eliminated by
making C3 large, the feedback circuit will enable faster operation of
the 567 by allowing C3 to be kept small. Note that if the feedback
time constant is made quite large, a short burst at the input
frequency can be stretched into a long output pulse. This may be
useful to drive, for example, stepping relays.
Although a large value of C2 will reduce the bandwidth, it also
reduces the loop damping so as to slow the circuit response time.
This may be undesirable. Bandwidth can be reduced by reducing
the loop gain. This scheme will improve damping and permit faster
operation under narrow-band conditions. Note that the reduced
impedance level at terminal 2 will require that a larger value of C2 be
used for a given filter cutoff
frequency. If more than three 567s are to be used, the network of RB
and RC can be eliminated and the RA resistors connected together.
A capacitor between this junction and ground may be required to
shunt high frequency components.
OUTPUT LATCHING (Figure 7)
To latch the output on after a signal is received, it is necessary to
provide a feedback resistor around the output stage (between Pins 8
and 1). Pin 1 is pulled up to unlatch the output stage.
DETECTION BAND CENTERING (OR SKEW)
ADJUSTMENT (Figure 5)
REDUCTION OF C1 VALUE
For precision very low-frequency applications, where the value of C1
becomes large, an overall cost savings may be achieved by
inserting a voltage-follower between the R1 C1 junction and Pin 6,
so as to allow a higher value of R1 and a lower value of C1 for a
given frequency.
When it is desired to alter the location of the detection band
(corresponding to the loop capture range) within the lock range, the
circuits shown above can be used. By moving the detection band to
one edge of the range, for example, input signal variations will
expand the detection band in only one direction. This may prove
useful when a strong but undesirable signal is expected on one side
or the other of the center frequency. Since RB also alters the duty
cycle slightly, this method may be used to obtain a precise duty
cycle when the 567 is used as an oscillator.
April 15, 1992
PROGRAMMING
To change the center frequency, the value of R1 can be changed
with a mechanical or solid state switch, or additional C1 capacitors
may be added by grounding them through saturating NPN
transistors.
412
Philips Semiconductors Linear Products
Product specification
Tone decoder/phase-locked loop
NE/SE567
TYPICAL APPLICATIONS
+
R3
567
897Hz
DIGIT
1
R2
C3
R1
C1
+
C2
2
3
567
770Hz
4
+
5
6
567
852Hz
7
8
+
9
567
941Hz
0
+
*
567
1209Hz
NOTES:
+
Component values (Typical)
R1 = 26.8 to 15kΩ
R2 = 24.7kΩ
567
1336Hz
R3 = 20kΩ
C1 = 0.10mF
+
C2 = 1.0mF 5V
C3 = 2.2mF 6V
C4 = 250µF 6V
567
1477Hz
Touch-Tone Decoder
April 15, 1992
413
Philips Semiconductors Linear Products
Product specification
Tone decoder/phase-locked loop
NE/SE567
TYPICAL APPLICATIONS (Continued)
+5 TO 15V
60Hz AC LINE
50–200VRMS
LOAD
5
C4
27pF
3
5
500pF
567
6
2
–
K1
1
+
6
+
R1
1:1
567
R1
8
5741
C1
2.5kΩ
fO ≈ 100kHz
C2
.006
C1
0.004mfd
Precision VLF
AUDIO OUT
(IF INPUT IS
FREQUENCY
MODULATED)
C3
.02
+V
Carrier-Current Remote Control or Intercom
3
567
5
6
8
2
1
+V
R1
INPUT SIGNAL
(>100mVrms)
C2
20k
f1
3
567
5
6
C1
8
2
C3
1
RL
R1
3
NOR
INPUT
CHANNEL
OR RECEIVER
C1
C2
C3
+V
VO
5
5
6
2
1
8
567
3
6
8
R’1
20k
f2
567
2
1
C’2
C’1
R’1
130
CȀ 2 + C 2 +
(mfd)
f
O
CȀ 1 + C 1
RȀ 1 + 1.12R 1
24% Bandwidth Tone Decoder
C’1
C’2
C’3
100mv (pp)
SQUARE OR
50mVRMS
SINE INPUT
OUTPUT
(INTO 1k
OHM MIN.
LOAD)
567
3
2
Dual-Tone Decoder
5
f2
6
R1
+90°
PHASE
SHIFT
C2
C1
NOTES:
R2 = R1/5
Adjust R1 so that φ = 90° with control midway.
0° to 180° Phase Shifter
NOTES:
1. Resistor and capacitor values chosen for desired frequencies and bandwidth.
2. If C3 is made large so as to delay turn-on of the top 567, decoding of sequential (f1 f2) tones is possible.
April 15, 1992
414
Philips Semiconductors Linear Products
Product specification
Tone decoder/phase-locked loop
NE/SE567
TYPICAL APPLICATIONS (Continued)
+
+
RL
567
3
RL
567
8
567
2
8
6
5
80°
2
6
5
2
6
5
3
CONNECT PIN 3
TO 2.8V TO
INVERT OUTPUT
fO
RL > 1000Ω
R1
VCO
TERMINAL
(±6%)
R1
R1
10k
C1
C2
C1
C2
CL
Oscillator With Quadrature Output
RL > 1000Ω
Oscillator With Double Frequency
Output
Precision Oscillator With 20ns
Switching
+
+
567
RL
567
3
6
6
5
567
1
5
OUTPUT
RL
8
8
1kΩ (MIN)
2
6
5
1
10kΩ
VCO
TERMINAL
(±6%)
R1
100kΩ
R1
C2
C1
C1
C1
Pulse Generator With 25% Duty Cycle
April 15, 1992
Precision Oscillator to Switch 100mA
Loads
415
DUTY
CYCLE
ADJUST
Pulse Generator