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8 7 6 5 4 3 2 1 IT8705F APPLICATION CIRCUIT SH1:IT8705F SH2:FDC,LPT & COM,IR & CIR SH3:FLASH ROM & VID CONTROL SH4:GAME ,MIDI & SMART CARD READER SH5:THERMISTOR & VOLTAGE MONITOR & FAN CONTROL SH6:LAYOUT/ROUTING GUIDELINES D D REVISION HISTORY SCHEMATICS PCB DATE REVISION MODIFICATION ITEM DRAWING AND P.C.B. MODIFICATION DESCRIPTION REVISION ITSA-CG-98017 VER 0.1 Oct.28,98 Subject : IT8705F ADD-ON CARD APPLICATION CIRCUIT. May.31,99 The Trace Between IT8712(Pin44) &Oscillator(output) Must Thicken and shorten. In Addition to That, The trace spacing must broaden. (SH1.SCH) FIRST DRAFT C C ITSA-CG-98017 VER 0.2 ISOLATED THE VBAT & SIS960 VCCRTC (SH1.SCH) ADD JUMPER FOR FA18 & MIDI SELECTION (SH1.SCH) CIR CONNECTOR ADD OPTIONAL POWER VCCH (SH2.SCH) ADD POWER ON STRAP & FLASH ROM UP TO 4M (SH3.SCH) RN9 PIN1 CONNECT TO +3VSB (SH4.SCH) ADD MIDI FUNCTION (SH4.SCH) CHANGE R45,R48,R50 RESISTOR FROM 510 TO 51(SH5.SCH) ADD PULL UP RESISTOR R59,R60,R61 (SH5.SCH) ADD RESERVED RESISTOR R62 (SH5.SCH) CHANGE C42,C43,C44 CAP FROM 0.1UF TO 3300pF (SH5.SCH) DELETE KEYLOCK# FUNCTION (SH1.SCH & SH5.SCH) ADD LDRQ# PULL HIGH TO 3.3V 4.7K PAGE SH1 R80 B B FD[0..7] PULL HIGH TO 5V 8.2K PAGE SH3 RP21.RP22 IT-8705-CG-S01 V1.1 VER 1.1 May.23,2000 ADD Smart Card Reader Function (SH1.SCH & SH4.SCH) IT-8705-CG-S01 V1.2 VER 1.2 Aug.22,2000 CHANGE Smart Card pin SCRPRES# Pull-up from VCCH to VCC (SH4.SCH) Add Flash ROM Pull Down Resistor (SH3.SCH) IT-8705-CG-S01 V1.3 VER 1.3 Mar.02,2001 IT-8705-CG-S01 V2.0 Change C37 and C41 from 0.1uF to 1uF (SH5.SCH) Add VID control Circuit (SH3.SCH) ADD Smart Card Reader Function ( SH4.SCH Block E) April.26,2001 VER 2.0 ADD layout guideline for I/O clock(SH6.SCH) A A Preliminary ITE Title IT8705F APPLICATION CIRCUIT NOTE: 8 Specification Subject to Change Without Notice. 7 6 5 4 3 Size B Document Number IT-8705-CG-S01 V2.0 Date: Thursday, April 26, 2001 2 Rev 2.0 Sheet 1 of 1 7 8 7 3 3 3 3,4 3,4 3 3,4 3 3 3 3 6 5 PD[0..7] STB# AFD# ERR# INIT# SLIN# ACK# GNDA 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 DTR2# RTS2# DSR2# 3,4 3 4 C GND FA0 FA1 FA2 FA3 FA4 FA5 FA6 FA7 FA8 FA9 FA10 FA11 FA12 FA13 FA14 FA15 FA16 FA17 FD[0..7] FD[0..7] 4 VCC TXD2 RXD2 FD0 FD1 FD2 FD3 FD4 FD5 FD6 FD7 TXD2 RXD2 FA[0..17] FA[0..17] +3.3V R80 4.7K VCC FRD# LDRQ# SERIRQ LAD0 BUSY PE SLCT VCC VIN0 VIN1 VIN2 VIN3 VIN4 VIN5 VIN6 VIN7 VREF TMPIN1 TMPIN2 TMPIN3 GNDA CIRRX/MIDI_IN/GP67 CIRTX/MIDI_OUT/GP66 IRRX/GP65 IRTX/GP64 PME#/GP63/SCRPRES# FAN_CTL3/GP62/SCRPFET# FAN_CTL2/GP61/SCRPRES# FAN_CTL1/GP60 VCCH VBAT FAN_TAC3/FA18/GP57/SCRPRES# FAN_TAC2/GP56/SCRPRES# FAN_TAC1/GP55 DSKCHG# WPT# INDEX# TRK0# RDATA# GNDD WGATE# HDSEL# SCRPFET# Pin59 R1 4.7K LRESET# LFRAME# PIN47 4 FWE# 5 SCRCLK 4 FCS# 5 SCRIO 1 2 3 PIN61 CON3 J5 3 3 3 3 3 3 3,5 MOTEB# 5 SCRRST 1 2 3 PIN59 CON3 J7 BUSY PE SLCT 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 CON3 BUSY PE SLCT 3 3 3 VIN0 VIN1 VIN2 VIN3 VIN4 VIN5 VIN6 VIN7 VREF TMPIN1 TMPIN2 TMPIN3 6 6 6 6 6 6 6 6 6 VCC 6 FAN_TAC2 CON3 5 SCRPRES# 1 2 3 PIN74 J10 5 SCRPRES# CON3 GNDA PIN85 PIN84 IRRX IRTX PIN81 PIN80 PIN79 FAN_CTL2 5 SCRPRES# 1 2 3 PIN79 PME# 5 6 6 6 CON3 L1 C 3 A 3 FAN_CTL1 VCCH 6 FAN_TAC1 DSKCHG# 3 WPT# 3 INDEX# 3 TK00# 3 RDATA# 3 WGATE# SIDE1# 6 3 3 BAT1 JP2 JOY8 JOY7 JOY6 JOY5 JOY4 JOY3 JOY2 JOY1 5 5 5 5 5 5 5 5 1 2 3 SCRPRES# FB GND 3 3 3 J11 PIN81 CON3 IRRX IRTX VCCH VBAT PIN75 PIN74 STEP# DIR# WDATA# 5 DRVA# 5 MOTEA# DENSEL# CON3 R89 4.7K TO SiS630 J9 6 1 2 3 PIN75 SB3V VIN0 VIN1 VIN2 VIN3 VIN4 VIN5 VIN6 VIN7 VREF D 1 2 3 PIN47 SCRPRES# PIN SELECT J8 1 2 3 PC Board Layout Checklist .Place C6 close to IT8705 .Recommended net "VBAT" minimum trace width 12mils .Isolated the VBAT pin76 & SIS630 RTCVDD(or SIS540) 3 + 2 1N4148 C5 LI-BAT 4.7UF/10V tantalum cap. (Spare for battery installation glitch) SIP\3P B 3 3 PCICLK +3.3V DRVB# 1 Pin61 LAD[0..3] 5 J6 3,5 D1 LAD3 LAD2 LAD1 B LAD[0..3] 1 1 2 3 PIN80 IT8705 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 4 DTR2#/JP4 RTS2# DSR2# VCC SOUT2/JP5 SIN2 FD0/MIDI_IN/GP10 FD1/MIDI_OUT/GP11 FD2/GP12 FD3/GP13 FD4/GP14 FD5/GP15 FD6/GP16 FD7/GP17 GNDD FA0/VID_IN0/GP20 FA1/VID_IN1/GP21 FA2/VID_IN2/GP22 FA3/VID_IN3/GP23 FA4/VID_IN4/GP24 FA5/VID_OUT0/GP25 FA6/VID_OUT1/GP26 FA7/VID_OUT2/GP27 FA8/VID_OUT3/GP30 FA9/VID_OUT4/GP31 FA10/GP32 FA11/GP33 FA12/GP34 FA13/GP35 FA14/GP36 FA15/GP37 FA16/GP50 FA17/GP51 FRD#/GP52 VCC LDRQ# SERIRQ LAD0 CTS2# RI2# DCD2# SIN1 SOUT1/JP3 DSR1# RTS1#/JP2 DTR1#/JP1 CTS1# RI1# DCD1# GNDD PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 STB# AFD# ERR# INIT# SLIN# ACK# 3,4 3 3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 FAN_CTL3 U1 LAD1 LAD2 LAD3 PCICLK GND CLKIN LRESET# LFRAME# FCS#/GP53/SCRIO FWE#/GP54 JSACX/GP40 JSACY/GP41 JSAB1/GP42 JSAB2/GP43 JSBCX/GP44 JSBCY/GP45 JSBB1/GP46 JSBB2/GP47 DENSEL# MTRA# MTRB#/SCRRST DRVA# DRVB#/SCRCLK WDATA# DIR# STEP# A 6 3 STB# AFD# ERR# INIT# SLIN# ACK# GND DTR2# RTS2# DSR2# 2 J4 PD[0..7] PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 VCC 3 SMART CARD READER JUMPER SELECT VCC D 4 DCD1# RI1# CTS1# DTR1# RTS1# DSR1# TXD1 RXD1 DCD2# RI2# CTS2# DCD1# RI1# CTS1# DTR1# RTS1# DSR1# TXD1 RXD1 DCD2# RI2# CTS2# C6 0.1UF JP20 6 FAN_TAC3 4 FA18 FAN_TAC3 PIN75 FA18 VCC 1 2 3 JP18 3 CIRTX 4,5 MIDIOUT CIRTX PIN84 MIDIOUT 1 2 3 SIP\3P SIP\3P VCC JP19 OSC1 1 C1 0.1UF 2 NC GND VCC 4 OUT 3 CLKIN C54 CAP OSC (24MHz or 48MHz) A VCC CLKIN Layout: The Trace Between IT8705(Pin44) & Oscillator(output) Must be Thicken and Shorten. In addition to that,The Trace Spacing Must be Broaden 3 CIRRX 4,5 MIDIIN CIRRX PIN85 MIDIIN 1 2 3 VCC C4 0.1UF SIP\3P C3 0.1UF SH1.SCH C2 0.1UF GND ITE * 8 NOTE: For Reference Only Specification Subject to Change Without Notice. 7 6 5 Title IT8705F 4 3 Size B Document Number IT-8705-CG-S01 V2.0 Date: Thursday, April 26, 2001 2 Rev 2.0 Sheet 2 of 1 7 A 8 7 6 5 4 3 2 1 VCC IR1 2 IRRX 2 IRTX 1 2 3 4 5 IRRX IRTX U2 VCCH 2 2 R8 4.7K SIP\5P JP21 SIP\3P 1 2 3 D VCC R5 2,4 2,4 2 2,4 2 D3 Q1 2N7002 NRI1# VCCH 2 R4 10K 10K -12V D4 1N4148 2 CIRRX 2 CIRTX CIRRX CIRTX RY1 RY2 RY3 DA1 DA2 RY4 DA3 RY5 RA1 RA2 RA3 DY1 DY2 RA4 DY3 RA5 2 3 4 5 6 7 8 9 11 10 GND -12V 5V 12V 20 1 2 2 2 2,4 2 2,4 2 RING# SIP\5P DCD2# DSR2# RXD2 RTS2# TXD2 CTS2# DTR2# RI2# DCD2# DSR2# RXD2 RTS2# TXD2 CTS2# DTR2# RI2# 19 18 17 16 15 14 13 12 11 10 VCC R2 NDCD1# NDSR1# NRXD1 NRTS1# NTXD1 NCTS1# NDTR1# NRI1# VCC D D2 +12V IN4001 U3 2 TO CHIPSET GD75232 19 18 17 16 15 14 13 12 IN4001 CIR1 1 2 3 4 5 DCD1# DSR1# RXD1 RTS1# TXD1 CTS1# DTR1# RI1# DCD1# DSR1# RXD1 RTS1# TXD1 CTS1# DTR1# RI1# GD75232 RY1 RY2 RY3 DA1 DA2 RY4 DA3 RY5 RA1 RA2 RA3 DY1 DY2 RA4 DY3 RA5 GND -12V 5V 12V NDCD2# NDSR2# NRXD2 NRTS2# NTXD2 NCTS2# NDTR2# NRI2# 2 3 4 5 6 7 8 9 20 1 150 RN1 8 6 4 2 Q2 2N7002 R6 7 5 3 1 NRI2# 10K R7 10K COM1 NDCD1# NTXD1 D5 1N4148 1 3 5 7 9 NRTS1# NRI1# 8P4R-150 CN1 C 2 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 DENSEL# 2 2 2,5 2 2,5 INDEX# MOTEA# DRVB# DRVA# MOTEB# DIR# STEP# WDATA# WGATE# TK00# WPT# RDATA# SIDE1# DSKCHG# 2 2 2 2 2 2 2 2 2 INDEX# MOTEA# DRVB# DRVA# MOTEB# DIR# STEP# WDATA# WGATE# TK00# WPT# RDATA# SIDE1# DSKCHG# REDWC NC NC INDEX MOTSA DRVSB DRVSA MOTEB DIR STEP WDATA WGATE TK00 WPT RDATA SIDE1 DSKCHG GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND COM2 NDCD2# NTXD2 VCC R3 2 2 2 STB# AFD# INIT# SLIN# ERR# 2 PD[0..7] 1 3 5 7 8P4R-2K 8P4R-22 STB# AFD# INIT# SLIN# ERR# PD[0..7] ACK# BUSY PE SLCT ACK# BUSY PE SLCT 2 2 8 6 4 2 RN3 2 4 6 8 8P4R-2K 1 3 5 7 1 3 5 7 2 4 6 8 RN7 2 4 6 8 RN8 2 4 6 8 B STROBE# AUTOFD# INITA# SLCTIN# ERR# AUTOFD# INITA# SLCTIN# ERR# CN2 PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 2 2 RN2 1 3 5 7 RN6 8P4R-2K VCC GND 2 2 NRXD2 NDTR2# NDSR2# NCTS2# 2 4 6 8 10 COM-P VCC B 1 3 5 7 9 NRTS2# NRI2# D6 1N4148 2K 7 5 3 1 C COM-P 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 FDC-CONN 8P4R-2K NRXD1 NDTR1# NDSR1# NCTS1# 2 4 6 8 10 8P4R-22 8P4R-22 2 4 6 8 2 4 6 8 RN4 STROBE# PPD0 PPD1 PPD2 PPD3 PPD4 PPD5 PPD6 PPD7 ACK# BUSY PE SLCT 1 3 5 7 1 3 5 7 RN5 1 2 3 4 5 6 7 8 9 10 11 12 13 STB PPD0 PPD1 PPD2 PPD3 PPD4 PPD5 PPD6 PPD7 ACK BUSY PE SLCT AFD ERROR INIT SLIN GND GND GND GND GND GND GND GND N/C 14 15 16 17 18 19 20 21 22 23 24 25 26 PRINT-FEM GND C10 C11 C12 C13 C14 C15 C16 C17 180PF 180PF 180PF 180PF 180PF 180PF 180PF 180PF C20 C19 C21 C7 C8 C9 C18 C22 C23 180PF 180PF 180PF 180PF 180PF 180PF 180PF 180PF 180PF A SH2.SCH ITE * 8 NOTE: Title For Reference Only Specification Subject to Change Without Notice. 7 6 5 I/O CONNECTOR 4 3 Size B Document Number IT-8705-CG-S01 V2.0 Date: Thursday, April 26, 2001 2 Rev 2.0 Sheet 3 of 1 7 A 8 7 FA[0..16] 2 FD[0..7] 5 4 3 VCC A FLASH ROM POWER ON STRAPS R11 1 2 3 DTR1# 2.2K VCC JP5 R13 2,3 2.2K R12 2,3 2.2K SIP\3P U4 FA16 FA15 FA14 FA13 FA12 FA11 FA10 FA9 FA8 FA7 FA6 FA5 FA4 FA3 FA2 FA1 FA0 JP6 VCC 1 2 3 RTS1# R14 2,3 SIP\3P JP8 1 2 3 DTR2# 2.2K SIP\3P VCC R63 2,3 TXD2 2.2K JP22 1 2 3 SIP\3P POWER ON STRAPS SETTING 2 2 2 R9 2 1-2 SHORT C RP22 8.2K D 1 2 3 TXD1 SIP\3P VCC RP21 8.2K JP7 2 4 6 8 2 4 6 8 VCC 2,3 1 FA[0..16] FD[0..7] D 2 1 3 5 7 1 3 5 7 2 6 FA17 FA17 VCC 2-3 SHORT FWE# FRD# FCS# 2 3 29 28 4 25 23 26 27 5 6 7 8 9 10 11 12 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 31 24 22 30 WE# OE# CE# PWD# 0 D0 D1 D2 D3 D4 D5 D6 D7 13 14 15 17 18 19 20 21 FD0 FD1 FD2 FD3 FD4 FD5 FD6 FD7 FA18 VPP JP5 FFFF0000h~FFFFFFFFh,FFFE0000h~FFFEFFFFh DISABLE FLASH ROM VCC JP24 4.7K SIP\3P JP6 FFEF0000h~FFEFFFFFh,FFEE0000h~FFEEFFFFh --------- JP7 FFF80000h~FFFDFFFFh,FFFE0000h~FFFEFFFFh --------- JP8 000F0000h~000FFFFFh,000E0000h~000EFFFFh --------- C24 0.1UF ENABLE 4M FLASH ROM NOTE: Do not populate if IT8705's pin47 is selected to FCS#. HEADER 3 +12V Select A or B circuit. A and B circuit can not populate simultaneously. --------- VCC B 1 2 3 R90 0 +12V JP22 C HEADER 3 R10 1 2 3 --------- 2 1 2 3 1 28F001BX-T JP4 Enable FLASH ROM ADDRESS SEGMENT FA18 JP23 B If select A circuit, B VID CONTROL 1 3 5 7 1 3 5 7 1 3 5 7 MIDIIN and MIDIOUT can not select IT8705's pin7 and pin8 . VCC 4.7K 4.7K RP23 RP24 4.7K RP25 2 4 6 8 2 4 6 8 2 4 6 8 MIDI Pin Select JP25 FA0 FA1 FA2 FA3 FA4 If select B circuit, A 1 3 5 7 9 2 4 6 8 10 VID_IN0 VID_IN1 VID_IN2 VID_IN3 VID_IN4 From CPU VID_OUT0 VID_OUT1 VID_OUT2 VID_OUT3 VID_OUT4 To PWM DC-DC Converter SIP\2P JP27 FD0 MIDIIN MIDIIN 2,5 MIDIOUT 2,5 HEADER 5X2 all flash ROM interface must be disable. (JP5,JP6,JP7,JP8,JP22 Pin 2-3 short) MIDIIN and MIDIOUT can select IT8705's pin7 and pin8 or others. JP26 FA5 FA6 FA7 FA8 FA9 1 3 5 7 9 2 4 6 8 10 HEADER 5X2 SIP\2P JP28 FD1 MIDIOUT A ITE SH3.SCH * 8 7 For Reference Only NOTE: Specification Subject to Change Without Notice. 6 5 4 3 Title FLASH ROM AND VID CONTROL Size B Document Number IT-8705-CG-S01 V2.0 Date: Thursday, April 26, 2001 2 Rev 2.0 Sheet 4 of 1 7 8 7 6 5 4 3 2 1 Smart Card Reader 2 JOY1 2 JOY2 2 D JOY5 2 JOY6 JOY1 R15 2.2K JOYA1 JOY2 R16 2.2K JOYA2 JOY5 R17 2.2K JOYB1 JOY6 R18 C29 0.01u C30 0.01u C31 0.01u 2.2K PIN TYPE MUST MATCH PHYSICAL LAYOUT VCC C JOYB2 CN3 2 2 1 2 3 4 5 6 7 SCRPFET# SCRCLK C32 0.01u VCC NC SCRFET# SCRCLK RFU GND NC LED NC SCRREST RFU SCRIO SCRPRES# NC 8 9 10 11 12 13 14 SCRRST D 2 SCRIO SCRPRES# 2 2 SMCARDCN VCC R81 4.7K VCC R19 4.7K 2 JOY3 2 JOY4 R20 4.7K R21 4.7K R22 4.7K +5V JOY3 JOYA3 JOY4 JOYA4 JOY7 JOYB3 JOY8 JOYB4 D 2 C JOY7 2 JOY8 OPEN R83 4.7K Q11 2N7002 R82 2 R88 SCRPFET# CN4 SMCARD 33 C61 .1UF C60 10UF R84 4.7K R85 4.7K C1I C2I C3I C4I R86 4.7K C33 0.001u C34 0.001u C K1 K2 C36 0.001u C5I C6I C7I C8I C35 0.001u 2 2 SCRRST SCRCLK SCRIO 2 VCC VCC R87 4.7K R66 4.7K VCC 2 SCRPRES# P1 R64 MIDIIN MIDIIN NMIDIIN JOYA4 JOYB4 JOYA2 JOYB2 470 R65 B 2,4 MIDIOUT MIDIOUT MIDIOUT JOYB1 JOYA1 JOYB3 JOYA3 470 C55 0.001U C56 0.001U E VCC_3 R91 B GPIO 2 SCRRST 2 33 R92 SCRCLK 4.7K R93 4.7K 1 2,4 8 15 7 14 6 13 5 12 4 11 3 10 2 9 1 DB15 2 2 Pin59 Joystick & MIDI 3 U1A 74125 MOTEB# 2,3 DRVB# 2,3 VCC +12V VCC -12V +12V -12V VCC GND BC1 10UF C25 10UF C26 10UF C27 10UF C28 10UF 1 BC2 10UF A 2 2 Pin61 3 U2A 74125 SH4.SCH ITE, Inc. For Reference Only Title Game & Smart Card Reader Connector * NOTE: Specification Subject to Change Without Notice. Size Date: 8 7 6 5 4 3 Document Number Custom IT-8705-CG-S01 V2.0 Thursday, April 26, 2001 2 Rev 2.0 Sheet 5 of 1 7 A 8 7 6 5 4 3 VCORE1 VCORE2 2 VCC3 VCC 1 +12V -12V -5V VCCH FAN Input and Output R29 10k_1% D R46 4.7K 2 2 2 2 2 2 2 2 +12V VCC R44 R59 4.7K 2N7002 Q6 2 R42 OPEN 1K FAN HEADER1 Q5 2N3906 R45 51 R32 6.8k_1% R33 30k_1% R34 232k_1% R35 120k_1% R38 56k_1% R39 56k_1% R40 6.8k_1% VIN0 VIN1 VIN2 VIN3 VIN4 VIN5 VIN6 VIN7 1 2 3 C51 22UF R43 10K R31 10k_1% J1 VCC FAN_CTL1 D R30 10k_1% R36 10k_1% R62 REV R37 10k_1% CON3 A R41 10k_1% A A 2 A FAN_TAC1 2 C57 CAP REV VREF C50 0.1UF C C45 0.1UF C46 0.1UF C47 0.1UF C48 0.1UF C49 0.1UF C A R56 4.7K +12V Thermal Diode layout notice: a.Place T.D. close to IT8705F b.Keep the trace away from: +12V, Fast data bus, CRTs. c.Recommanded trace widths & spacings is 10 miles. VCC R51 OPEN R47 R60 4.7K 1K 2N7002 Q7 2 R48 51 C52 22UF R54 10K 2 J2 VREF 1 2 3 VCC FAN_CTL2 2 FAN HEADER2 Q9 2N3906 R26 30K 1% R27 30K 1% R28 30K 1% CON3 2 2 2 FAN_TAC2 TMPIN1 TMPIN2 TMPIN3 C58 CAP REV D+ C44 B C41 1UF Q3 2N3904 Q4 2N3904 C43 3300pF 3300pF 2 B FROM PII CPU C42 3300pF D- A Choosing method of measuring temperature by either thermistor or diode R53 4.7K 2 +12V VREF R23 10K 1% VCC R49 R61 4.7K 1K 2N7002 Q8 2 FAN_CTL3 2 2 2 J3 1 2 3 C53 22UF R55 10K R24 10K 1% R25 10K 1% FAN HEADER3 Q10 2N3906 VCC R50 51 2 R52 OPEN TMPIN1 TMPIN2 TMPIN3 RT1 TR10K RT2 TR10K RT3 TR10K C40 CON3 C37 1UF .1UF C39 .1UF t t C38 .1UF t FAN_TAC3 A C59 CAP REV SH5.SCH A VCC ITE VCC For Reference Only GNDA GND GNDA Title THERMAL CONTROL Specification Subject to Change Without Notice. A 8 7 6 5 4 3 Size B Document Number IT-8705-CG-S01 V2.0 Date: Thursday, April 26, 2001 2 Rev 2.0 Sheet 6 of 1 7 A 8 7 6 5 4 3 2 1 LAYOUT/ROUTING GUIDELINES 1.For CLOCK LINES, 1)If possible, please avoid using any through-hole. 2)Please make the trace length short, and the trace width wide enough. 3)The spacing to the closest neighbor should be wide enough. D D 4)The discrete damping resistors and capacitors are recommended. 5)Please don't share I/O( 24M or 48M) with other devices. 2.For the VBAT circuits, 1)Place the 1u capacitor of Vbat pin close to ITE I/O chip. 2)Vbat should be routed with a minimum trace width of 12 mils. 3)Isolate the Vbat pin of ITE I/O chipfrom the pin pinG1/VCCRTC of intel ICH with diode. 4)The 4.7u/10V tantalum capacitor connected to the diode of battery is spare for battery installation glitches. 3.Please don't remove the pull-up resistor of LDRQ#. 4.Please don't change the resistors and capacitors values in the Game and MIDI circuits. C C For HARDWARE MONITOR 5.Please reserve an area for Analog Ground on your board. Moreover, connect the D- of CPU Thermal Diode and other components should be connected with AGND to this area. 6.For the temperature sensor circuits, 1)Please don't remove the 1u capacitor between Vref and AGND. 2)Place the thermal diode close to ITE I/O chip. 3)Keep the trace away from +12V, fast data bus, and CRTs. 4)Recommended trace widths and spacings are 10 mils. B 5)Isolate AGND and DGND. 7.Please don't remove any components in the VINx circuits and the FANx control circuits. B 8.For the SmartGuardian software compatibility, 1)Please don't change the sequence of VIN0~VIN7. 2)Please let FAN_CTL1/FAN_TAC1 circuit control and report the specific temperture which is detected by TMPIN1, let FAN_CTL2/FAN_TAC2 circuit control and report the specific temperature which is detected by TMPIN2, and let FAN_CTL3/FAN_TAC3 circuit control and report the specific temperature which is detected by TMPIN3. 9.If you would like to ignore some voltage monitoring,for example,-12V,please pull it down to GND.Don't leave it floating. A 10.If the power supply is specially designed,not ATX supply,for example,every provided voltage is transferred from +12V,please note the leakage current problem caused from the standby voltages monitoring.This is due to the chip inside power plane of whole H/W Monitor is Vcc,not 5V standby.When Vcc is OFF and standby voltages are ON,the leakage will happen at the corresponding VINx pins pins from the monitored standby voltage sources. 8 7 6 5 4 SH6.SCH A ITE Title Layout/routing guidelines 3 Size B Document Number IT-8705-CG-S01 V2.0 Date: Thursday, April 26, 2001 2 Rev 2.0 Sheet 7 of 1 7