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Application Note 117
April 2008
DC/DC µModule Regulator Printed Circuit Board
Design Guidelines
(LTM802x Series are used for this discussion)
By David Ng
The LTM8020, LTM8021, LTM8022 and LTM8023 μModules
are complete easy-to-use encapsulated step down DC/DC
regulators intended to take the pain and aggravation out
of implementing a switching power supply onto a system
board. With a μModule, you only need an input cap, output
cap and one or two resistors to complete the design. As
one might imagine, this high level of integration greatly
simplifies the task of printed circuit board design, reducing the effort to four categories: component footprint
generation, component placement, routing the nets, and
thermal vias.
Component Footprint Generation
One of the first things to do when designing a printed
circuit board is generate the footprint or decal for each
component. The components required to complete the
LTM8020, LTM8021, LTM8022 and LTM8023 designs
are common resistors and capacitors that have industry
standard footprints. The basic information necessary to
generate the footprint for a LTM8020, LTM8021, LTM8022
or LTM8023 is given in the package outline drawing, which
can be found in the “Package Description” section of the
data sheet, which is also accessible online at:
http://www.linear.com/designtools/packaging/index.jsp
It is indexed by package drawing number, which is also
found in the “Package Description” section of the data
sheet.
Next, choose a pad size in accordance with Linear Technology Application Note 100. For the LTM8020, LTM8021,
LTM8022, and LTM8023, square pads with sides measuring
between 0.025” and 0.029” will work for most applications.
Per the recommendations of the application note, make
the pads non-solder mask defined (NMSD), with a solder
mask expansion of zero to 0.002”, or 0.05mm.
The LTM80xx series of μModules have both I/O and power
connections. The I/O connections are typically routed with
a trace. The power and ground connections are usually
hooked up by laying planes. If the μModule footprint uses
a solder mask expansion of zero, all of the pads will be the
same size. If the solder mask expansion is greater than
zero, the power pads will be bigger than the I/O pads.
Take a moment to examine the pad pattern. Note that the
pads surrounding the VIN net have been depopulated.
The reason for this is because each of the LTM8020,
LTM8021, LTM8022 and LTM8023 μModules are rated
for 36VDC operation. According to IPC 2221, Generic
Standard on Printed Board Design, Table 6-1, uncoated
external printed circuit board conductors, such as solder
pads, with 31 to 50V between them must be separated
by at least 0.6mm, or 0.0236”. On the LTM80xx series of
μModules, the square pads are 0.025” on a side, placed at
a 0.050” pitch. If the μModule operates above 31V steady
state, the actual printed circuit board pad may not exceed
0.0257” before violating the IPC-2221 standard. In this
case, it is best to make the footprint pad opening 0.025”
NMSD with a zero solder mask expansion. If no adjacent
pins operate above 30V, any size pad with a net opening
between 0.025” and 0.029” will suffice.
Component Placement
In general, components should be placed which result in
traces that are as short as possible. There are very few
components to put down, and are located near the edge
of the device, which simplifies the design. For example,
on the LTM8020, the typical components are the μModule,
a single output voltage resistor, along with an input and
output cap. In order to keep the traces as short as possible,
place the set resistor RADJ adjacent to the ADJ pad, the
input cap CIN next to VIN and the output cap COUT next to
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All other trademarks are the property of their respective owners.
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Application Note 117
VOUT. An example of this is shown in Figure 1.
VOUT
VIN
CIN
keep output noise to a minimum, it is better to place COUT
as shown in Figure 3, where the GND connection of COUT
is farther away from that of CIN. There are large current
pulses flowing through CIN, so moving the COUT GND
connection away from that of CIN will reduce the coupling
between the two capacitors.
BIAS
RT
COUT
GND
ADJ
SHARE
RT
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GND
ADJ
SYNC
RADJ
PGOOD
Figure 1. LTM8020 Example Component Placement
RUN/SS
COUT
In the case of the LTM8022 and LTM8023, there are two
caps and two resistors. The component placement guidelines are very similar to those for the LTM8020. Place the
set resistor RADJ adjacent to the ADJ pad, the input cap
CIN next to VIN and the output cap COUT next to VOUT. The
remaining part, RT, needs to be placed as close as possible
to the μModule RT pad. This is shown in Figure 2.
RT
BIAS
VOUT
VIN
CIN
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Routing Nets
RT
ADJ
SYNC
GND
PGOOD
RUN/SS
AUX
AUX
Figure 3. Moving the COUT Capacitor Away from CIN
Can Reduce Output Noise
RADJ
SHARE
BIAS
VOUT
VIN
COUT
RADJ
CIN
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Figure 2. LTM8023 Example Component Placement
It is also possible to place the COUT capacitor in an alternate
position, where the GND connection is not so close to that
of CIN. In most applications, the location of COUT relative
to CIN is not critical. In circuits where it is important to
With the low number of components, and the components
placed so that the traces are as short as possible, the job of
routing nets is pretty straightforward. The task of routing
nets breaks down into routing traces and laying planes.
Traces are used to rout the low current nets. For the
LTM8023 example above, traces are used for everything
except the VIN, VOUT and GND nets. The RT and ADJ simply connect to the RT and RADJ resistors. The BIAS and
RUN/SS connections depend upon the specific design.
The LTM8022 and LTM8023 pad patterns are designed
with the layout in mind. In most applications, BIAS is
connected to either VAUX or VIN, so BIAS is conveniently
located for easy access to VAUX or VIN. Furthermore, for
those cases where a connection to external voltage source
is necessary, the BIAS pad is located adjacent to an edge
row, allowing easy access to external circuitry.
The RUN/SS pad is either connected to VIN or an external
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Application Note 117
signal source, so it is located next to the VIN pads on an
outer row. Figure 4 shows an example of the LTM8023
where BIAS is connected to VAUX and RUN/SS is connected
to VIN, and the RT and ADJ connections. The traces are
shown in gray. The remaining I/O pins, SHARE, SYNC and
PG, are also easily accessed.
RT
GND PLANE
GND
RADJ
SHARE
RT
ADJ
SYNC
PGOOD
RUN/SS
COUT
RT
GND
AUX
BIAS
RADJ
VOUT
SHARE
VIN
RT
ADJ
SYNC
PGOOD
CIN
RUN/SS
COUT
AUX
VOUT PLANE
VIN PLANE
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BIAS
Figure 5. Suggested Power and Ground Planes for LTM8023.
Note the Wide Gap that Separates the High Voltage VIN net From
Other Nets, in Compliance with IPC-2221
VOUT
VIN
and VIN nets are carried on multiple layers, vias should be
added to them, as well.
CIN
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Figure 4. The Placement of the I/O Pins
Makes Them Easy to Route.
Next, place the power and ground plane, which should
be as wide as possible for good thermal and EMI performance. As shown in Figure 5, these planes, shown in gray,
should together fill nearly all of the remaining copper area
underneath the μModule. In the example of Figure 5, there
is a wide gap between the VIN and other planes, which
applies for greater than 30V input voltages.
Thermal and Electrical Interconnect Vias
The last task is to place thermal and electrical interconnect
vias. The LTM8020, LTM8021, LTM8022 and LTM8023
μModules use the printed circuit board to spread the power
dissipated within the product, so it is important to place
vias underneath and around the μModule to distribute heat
throughout the layers of printed circuit board. In general,
a printed circuit board will have several ground planes,
so adding vias should be easily accomplished. If the VOUT
Most printed circuit board designs consider planes to be
both electrically and thermally equipotential. That is, the
voltage gradient across the plane is assumed to be an
ideal zero volts, and that the thermal resistance from a
point to any other point is negligible. This is not actually
true, especially from the thermal perspective, but using
vias is a simple and inexpensive way of achieving a design
whose performance approaches this ideal.
Figure 6 shows a layout example with interconnect vias on
the VIN, VOUT and GND planes. The vias are all the same
size, with a 0.010" drill hole and 0.015” outer diameter.
This sized via fits easily between pads of the same net,
and has a good current carrying capability. With careful
placement, vias with a 0.035” outer diameter may be used
without overlapping adjacent pads.
Vias act as very good electrical conductors to interior
planes and serve as heat pipes to allow the printed circuit
board to act as the heatsink. For the best performance
and reliability, the μModule should be operated as cool
as possible, so one might conclude that the best design
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Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
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Application Note 117
RT
GND PLANE
THERMAL
VIAs
GND
RADJ
SHARE
RT
ADJ
SYNC
PGOOD
RUN/SS
COUT
AUX
BIAS
has as many vias that will possibly fit. Each via, however,
starts as a hole drilled into the board, which reduces the
amount of copper that is present on the printed circuit
board layers for electrical conduction. It is thus possible to
have too many vias, so please consult your organization’s
design guidelines.
Conclusion
The high level of integration of the LTM8020, LTM8021,
LTM8022 and LTM8023 μModules simplifies the task of
the printed circuit board design for your power system.
The whole job can be summarized as four tasks as shown
in Table 1.
VOUT
VIN
CIN
VOUT PLANE
VIN PLANE
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Figure 6. Use Vias to Conduct Electrical Power to Internal
Planes and As Heat Pipes to Distribute Heat Throughout the
Printed Circuit Board.
Table 1. μModule Printed Circuit Board Design
TASK
DESCRIPTION/NOTES
Footprint Generation
• Get package outline drawing from the datasheet or http://www.linear.com/designtools/packaging/index.jsp
• If adjacent pins have greater than 30V, use 0.025” NSMD pads, otherwise, use 0.025” to 0.029” NSMD pads
• Use a solder mask expansion between zero and 0.002”
Component Placement
• Place components to keep trace lengths as short as possible
• Physically separate CIN and COUT GND connections if minimum switching noise required
Route Nets
• Use layout design features to minimize routing complexity
• Extend copper planes as far as practical for good EMI and thermal performance
Thermal and Electrical
Interconnect Vias
• Use vias to connect to internal layers
• Place vias to conduct heat to internal layers
• 0.010” ID, 0.015” OD fits between pads of the same net
• Up to 0.035” OD vias may be used for higher heat transfer with careful placement
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