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I/O Management
Course "Operating Systems"
Chapter 9
Prof. Dr.-Ing. Norbert Luttenberger
Research Group for Communication Systems
Dept. of Computer Science
Christian-Albrechts-University in Kiel
Overview
Informatik ∙ CAU Kiel
1. Categories of I/O devices
2. Organization of the I/O function
3. Device abstraction
4. I/O buffering
© N. Luttenberger
2
1. Categories of I/O Devices
Categories of I/O Devices
Informatik ∙ CAU Kiel
• An incomplete list of criteria
– Local or remote devices
– Device data rate
– Stream or block devices
– Sequential, direct access or random access devices
– Sharable or dedicated devices
– Read/write, read-only, or write-only devices
– Programmed I/O, interrupt-driven I/O, Direct Memory Access (DMA)
– Degree of device abstraction
– "Cooked" or "raw" devices
– …
© N. Luttenberger
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Categories of I/O Devices
Informatik ∙ CAU Kiel
• Local or remote
– Local
o
Monitor, keyboard, mouse, tablet, printer, …
o
Disk drives (hard disk, optical disk, flash drive)
o
USB devices
o
Sensors, actuators
– In-between
o
Network interfaces (wired, wireless)
o
modems
– Remote
o
© N. Luttenberger
all of the above
5
Categories of I/O Devices
Informatik ∙ CAU Kiel
• Device data rates
from: Tanenbaum, Woodhull:
Operating Systems—Design and Implementation.
2006, Prentice-Hall.
© N. Luttenberger
6
Categories of I/O Devices
Informatik ∙ CAU Kiel
• Device data rates
© N. Luttenberger
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Categories of I/O Devices
Informatik ∙ CAU Kiel
• Stream vs. block devices
– Stream devices
o
o
Transfer information as a stream of bytes
Terminals, printers, communication ports, mice and
other pointing devices
o
Most devices that are not secondary storage
o
Commands include get, put
o
Libraries layered on top allow line editing
© N. Luttenberger
8
Categories of I/O Devices
Informatik ∙ CAU Kiel
• Stream vs. block devices
– Block devices
o
Information is stored in fixed sized blocks.
o
Transfers are made a block at a time.
o
Used for disks and USB memory sticks
o
Commands include read, write, seek.
© N. Luttenberger
9
Categories of I/O Devices
Informatik ∙ CAU Kiel
• Data access mode
– sequential access
from: Wikipedia,
"sequential access"
o
group of data items is accessed in a
predetermined, ordered sequence
o
sometimes the only way of accessing the data
o
example: data on a tape drive
© N. Luttenberger
10
Categories of I/O Devices
Informatik ∙ CAU Kiel
• Data access mode
– random access
from: Wikipedia,
"random access"
o
o
o
© N. Luttenberger
The ability to access an arbitrary element of a sequence
in equal time.
Term mostly used for Random Access Memory (RAM):
semiconductor memory chips used in computers.
I/O device with similar capabilities:
flash memory on USB memory sticks
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Categories of I/O Devices
Informatik ∙ CAU Kiel
• Data access mode
– in-between: direct access
o
o
"A DASD (pronounced /ˈdæzdi/) is any secondary storage device
which has relatively low access time for all its capacity.
Term was introduced by IBM to cover three different device types:
disk drives, magnetic drums, and data cells. "
from: Wikipedia,
"direct access"
© N. Luttenberger
12
Categories of I/O Devices
Informatik ∙ CAU Kiel
• Sharable vs. dedicated devices
– Sharable
o
Sharable devices may be accessed by more than a single user.
– Dedicated
o
© N. Luttenberger
A dedicated device is dedicated to a single user.
13
Categories of I/O Devices
Informatik ∙ CAU Kiel
• Read/write, read-only, write-only devices
– Read/write
o
Device offers read and write access functions
o
Sample: disk
– Read-only
o
Read access only
o
Sample: CD-ROM
– Write-only
o
Write access only
o
Sample: printer
© N. Luttenberger
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2. Organization of the
I/O Function
Organization of the I/O Function
Informatik ∙ CAU Kiel
• A model for connecting CPU, memory, controllers,
and I/O devices
from: Tanenbaum, Woodhull:
Operating Systems—Design and Implementation.
2006, Prentice-Hall.
© N. Luttenberger
16
Organization of the I/O Function
Informatik ∙ CAU Kiel
© N. Luttenberger
from: Silberschatz, Galvin, Gagne:
Operating System Concepts with Java, 7th ed.
2007, Wiley.
• Another model for connecting CPU, memory, controllers,
and I/O devices
17
Organization of the I/O Function
Informatik ∙ CAU Kiel
• I/O techniques
– Programmed I/O
o
Process is busy-waiting for the operation to complete
– Interrupt-driven I/O
o
o
I/O command is issued,
processor continues executing instructions
Interrupt signals (un)successful completion of I/O operation
– Direct Memory Access (DMA)
o
o
© N. Luttenberger
DMA module controls exchange of data between main memory
and the I/O device
Processor interrupted only after entire block has been transferred
18
Organization of the I/O Function
Informatik ∙ CAU Kiel
• I/O techniques
© N. Luttenberger
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Organization of the I/O Function
Informatik ∙ CAU Kiel
• Programmed I/O
© N. Luttenberger
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Organization of the I/O Function
Informatik ∙ CAU Kiel
• Interrupt-driven I/O
– Classes of interrupts
Program
Generated by some condition that occurs as a result of an
instruction execution, such as arithmetic overflow, division by
zero, attempt to execute an illegal machine instruction, and a
reference outside a user's allowed memory space.
Timer
Generated by a timer within the processor. This allows the
operating system to perform certain functions on a regular
basis.
I/O
Generated by an I/O controller to signal normal completion of
an operation or to signal a variety of error conditions.
Hardware failure
Generated by a failure, such as power failure or
memory parity error.
© N. Luttenberger
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Organization of the I/O Function
Informatik ∙ CAU Kiel
Vector Description
Type
Error Code Source
•0 Interrupt
vector samples:
IntelNoprocessors
Divide Error (#DE)
Fault
DIV and IDIV instructions.
1
Debug (#DB)
Fault/Trap
No
Any code or data reference.
2
NMI
No
External interrupt.
3
Breakpoint (#BP)
Non-Maskable
Interrupt
Trap
No
INT3 instruction.
4
Overflow (#OF)
Trap
No
INTO instruction.
5
BOUND Range Exc. (#BR)
Fault
No
BOUND instruction.
6
Invalid Opcode (#UD)
Fault
No
UD2 instruction or reserved opcode.
7
Device Not Av. (#NM)
Fault
No
Floating-point or WAIT/FWAIT instruction.
8
Double Fault (#DF)
Abort
Yes (Zero)
9
CoProcessor Segment
Overrun (reserved)
Invalid TSS (#TS)
Fault
No
Fault
Yes
Any instruction that can generate an
exception, an NMI, or an INTR.
Floating-point instruction. Pentium Pro
processor does not generate this exception.
Task switch or TSS access.
10
© N. Luttenberger
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Organization of the I/O Function
Informatik ∙ CAU Kiel
Vector Description
Type
• 11
Interrupt
samples:
Segment Not vector
Present (#NP)
Fault
Error Code Source
IntelYesprocessors
Loading(cont'd.)
segment registers or accessing
12 Stack Fault (#SS)
Fault
Yes
13 General Protection (#GP)
Fault/Trap
Yes
14 Page Fault (#PF)
Fault
Yes
15 (Intel reserved. Do not use.)
system segments.
Stack operations and SS register loads.
Any memory reference and other protection
checks.
Any memory reference.
No
16 Floating-Point Error (#MF)
Fault
No
Floating-point or WAIT/FWAIT instruction.
17 Alignment Check (#AC)
Fault
Yes (Zero)
Any data reference in memory.
18 Machine Check (#MC)
Abort
Model
Dependent
Model dependent.
19-31 (Intel reserved. Do not use.)
32-255 Maskable Interrupts
© N. Luttenberger
Maskable
External interrupt or INT n instruction.
23
Organization of the I/O Function
Informatik ∙ CAU Kiel
from: Silberschatz, Galvin, Gagne:
Operating System Concepts with Java, 7th ed.
2007, Wiley.
• Interrupt-driven I/O
© N. Luttenberger
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Organization of the I/O Function
Informatik ∙ CAU Kiel
• Interrupt-driven I/O
– Star-shaped interrupt wiring
© N. Luttenberger
from: Silberschatz, Galvin, Gagne:
Operating System Concepts with Java, 7th ed.
2007, Wiley.
interrupt
controller
25
Organization of the I/O Function
Informatik ∙ CAU Kiel
• Interrupt-driven I/O: interrupt hardware
address/data bus
INTA
NMI
processor
interrupt
controller
(8259A)
…
INTR
external
interrupt
signals
1.
On interrupt, the interrupt controller asserts an INTR signal.
2.
In response, the processor provides two INTA cycles (INTerrupt Acknowledge).
3.
In second INTA cycle, the interrupt controller sends interrupt vector
via data bus (D0-D7).
© N. Luttenberger
26
Organization of the I/O Function
Informatik ∙ CAU Kiel
• Interrupt-driven I/O: interrupt hardware
INTR
8259A
INTA
Interrupt Service Register
Interrupt Mask Register
masking of interrupts
Interrupt Request Register
IR 0
7
– Signal on IR x line sets bit in Interrupt Request Register (IRR)
– IRR bit is forwarded to Interrupt Service Register (ISR) on INTA
unless masked by corresponding bit in Interrupt Mask Register
– ISR bit is cleared by issuing an EOI command to the controller
© N. Luttenberger
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Organization of the I/O Function
Informatik ∙ CAU Kiel
• On interrupt
– Suspend
execution of
program
– Execute
interrut handler
routine
© N. Luttenberger
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Organization of the I/O Function
Informatik ∙ CAU Kiel
• Changes
in memory
and registers
for an
interrupt
Program is interrupted
after execution of
instruction at location N.
© N. Luttenberger
increasing
addresses
increasing
addresses
Return from
interrupt.
29
Organization of the I/O Function
Informatik ∙ CAU Kiel
• Simple interrupt processing
mask interrupt
controller asserts
interrupt vector
© N. Luttenberger
send EOI to controller,
unmask interrupt
PSW
PC
Processor Status Word
Program Counter
30
Organization of the I/O Function
Informatik ∙ CAU Kiel
• Control flow: interrupts with short I/O wait
Time
© N. Luttenberger
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Organization of the I/O Function
Informatik ∙ CAU Kiel
• Control flow: interrupts with long I/O wait
Time
© N. Luttenberger
32
Organization of the I/O Function
Informatik ∙ CAU Kiel
• Direct Memory Access (DMA)
– Processor delegates I/O operation to the DMA module.
– DMA module transfers data directly to or form memory.
– After completion of the I/O operation
DMA module sends an interrupt signal to the processor.
© N. Luttenberger
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Organization of the I/O Function
Informatik ∙ CAU Kiel
• Direct Memory Access (DMA) (cont'd.)
– DMA controller block diagram
© N. Luttenberger
34
Organization of the I/O Function
Informatik ∙ CAU Kiel
• Direct Memory Access (DMA) (cont'd.)
– DMA operation
from: Tanenbaum, Woodhull:
Operating Systems—Design and Implementation.
© N. Luttenberger
2006, Prentice-Hall.
35
Organization of the I/O Function
Informatik ∙ CAU Kiel
• Direct Memory Access (DMA) (cont'd.)
from: Silberschatz, Galvin, Gagne:
Operating System Concepts with Java, 7th ed.
2007, Wiley.
– DMA operation
© N. Luttenberger
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Organization of the I/O Function
Informatik ∙ CAU Kiel
• DMA configurations
– single bus, detached DMA
– single bus, integrated DMA
© N. Luttenberger
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Organization of the I/O Function
Informatik ∙ CAU Kiel
• DMA configurations (cont'd.)
–
I/O bus
© N. Luttenberger
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Organization of the I/O Function
Informatik ∙ CAU Kiel
• Evolution of the I/O Function
1.
Processor directly controls a peripheral device
o
2.
Controller or I/O module is added
o
o
3.
Processor uses programmed I/O without interrupts
Processor does not need to handle details of external devices
Interrupt: Processor does not spend time waiting for an
I/O operation to be performed
Controller is given direct access to memory (DMA)
o
o
© N. Luttenberger
Blocks of data are moved into memory
without involving the processor
Processor involved at beginning and end only
39
Organization of the I/O Function
Informatik ∙ CAU Kiel
• Evolution of the I/O Function (cont'd.)
4.
I/O module has a separate processor and local memory
o
© N. Luttenberger
"I/O processor" or "I/O channel"
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3. Device Abstraction
Device Abstraction
Informatik ∙ CAU Kiel
• OS design issues
– Efficiency
o
o
Most I/O devices are extremely slow compared to main memory:
I/O cannot keep up with processor speed.
Use of multiprogramming allows for some processes to be waiting
on I/O while another process executes.
– Generality
o
Desirable to handle all I/O devices in a uniform manner
o
Hide most of the details of device I/O in lower-level routines
© N. Luttenberger
42
Device Abstraction
Informatik ∙ CAU Kiel
• Layered structure of an OS
from: Tanenbaum, Woodhull:
Operating Systems—Design and Implementation.
2006, Prentice-Hall.
© N. Luttenberger
43
from: Silberschatz, Galvin, Gagne:
Operating System Concepts with Java, 7th ed.
2007, Wiley.
Device Abstraction
Informatik ∙ CAU Kiel
• Layered structure of an OS
© N. Luttenberger
44
Device Abstraction
Informatik ∙ CAU Kiel
• Device-independent I/O software
© N. Luttenberger
45
Device Abstraction
Informatik ∙ CAU Kiel
• Uniform driver interface
non-uniform interface
uniform interface
from: Tanenbaum, Woodhull:
Operating Systems—Design and Implementation.
2006, Prentice-Hall.
© N. Luttenberger
46
Device Abstraction
Informatik ∙ CAU Kiel
• Additional software layers
– local peripheral device, reading/writing streams of bytes
User
process
Logical I/O
hides device-specific details, provides device ID,
simple interface: open, close, read, write, control
Device I/O
provides I/O buffers, issues appropriate I/O commands,
handles interrupts
Hardware
© N. Luttenberger
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Device Abstraction
Informatik ∙ CAU Kiel
• Additional oftware layers (cont'd.)
– secondary storage
User
process
File system,
dir. mgmt.
file name-to-disk location resolution, directory operations,
file operations: open, read, write, close, delete, …
Logical I/O
hides device-specific details, provides device ID,
simple interface: open, close, read, write, control
Device I/O
provides I/O buffers, issues appropriate I/O commands,
handles interrupts
Hardware
© N. Luttenberger
48
Device Abstraction
Informatik ∙ CAU Kiel
• Additional software layers (cont'd.)
– communication port
User
process
Protocol stack
correct transmission: no bit errors, no packet loss/duplication,
packets in sequence, local-to-network syntax translation, …
Logical I/O
hides device-specific details, provides device ID,
simple interface: open, close, read, write, control
Device I/O
provides I/O buffers, issues appropriate I/O commands,
handles interrupts
Hardware
© N. Luttenberger
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4. I/O Buffering
I/O Buffering
Informatik ∙ CAU Kiel
• No buffering
© N. Luttenberger
51
I/O Buffering
Informatik ∙ CAU Kiel
• Why should the OS provide data buffering
for user input/output data?
– Without OS buffering, user I/O would have to interfere with
OS paging decisions to avoid sequence of events as follows:
o
User process is blocked until end of I/O operation,
o
user process page is swapped out,
o
➜
I/O operation is blocked until buffer (i.e. page of the
blocked process) becomes available.
To avoid a "single-process" deadlock, the page providing
the input buffer must be locked in memory!
© N. Luttenberger
52
I/O Buffering
Informatik ∙ CAU Kiel
• OS assigns a buffer in main memory for an I/O request
– Block-oriented I/O
o
Input transfers made to buffer
o
Block moved to user space when needed
o
Another block is moved into the buffer: Read ahead
o
o
o
© N. Luttenberger
User process can process one block of data
while next block is read in
Swapping can occur since input is taking place
in system memory, not user memory
OS keeps track of assignment of system buffers
to user processes
53
I/O Buffering
Informatik ∙ CAU Kiel
• OS assigns a buffer in main memory for an I/O request
– Stream-oriented I/O
o
o
o
© N. Luttenberger
Used a line at time
User input from a terminal is one line at a time
with carriage return signaling the end of the line
Output to the terminal is one line at a time
54
I/O Buffering
Informatik ∙ CAU Kiel
• Double buffer
– A process can transfer data to or from one buffer while the operating
system empties or fills the other buffer
• Single buffer
© N. Luttenberger
55
I/O Buffering
Informatik ∙ CAU Kiel
• Circular buffer
– More than two buffers are used
– Each individual buffer is one unit in a circular buffer
– Used when I/O operation must keep up with process
© N. Luttenberger
56
Feedback for this Chapter
Informatik ∙ CAU Kiel
• Well understood –
easy material
• Mostly understood –
material is ok
• Hardly understood –
difficult material
© N. Luttenberger
57